Ring Oscillator Delay Circuit for PTV-Stable Variable Delays
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Solution Overview
Problem
Existing delay circuits are limited in their ability to provide fixed delays independent of voltage, temperature, and process variations, and struggle to simulate delays other than ¼th or ⅕th of a reference clock period, with limited frequency range and response time.
Innovation Solution
A delay circuit comprising a ring oscillator circuit and a counter circuit that generates delay codes by counting clock cycles and traversed delay elements, allowing for the simulation of various delays and compensation for Process Temperature Voltage (PTV) variations, using a combination of buffers and counters to store clock cycles and bit patterns corresponding to the number of delay elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay line uses a reference clock to calibrate fixed delay, then the delay is independent of voltage, temperature and process variations, but the frequency range is limited and response time to variations is limited
Solution Approach 1:
The delay line is configured to dynamically adjust its delay characteristics in response to PTV variations. The system transitions from a static fixed-delay approach to a dynamic adaptation mechanism that automatically recalibrates delay values based on detected variations, enabling both stability and adaptability across frequency ranges.
Solution Approach 2:
A feedback mechanism is implemented where the delay line monitors PTV variations and automatically adjusts its delay parameters. The system uses detected variations as feedback to recalibrate the delay elements, ensuring continuous accuracy across changing operating conditions and frequency ranges without manual intervention.
2Manufacturing precision
If a delay line is configured to provide fixed delay of 1/4th or 1/5th of reference clock period, then the delay is calibrated using reference clock, but fixed delays different from these values cannot be implemented
Solution Approach 1:
The delay line incorporates dynamic adjustment capability that allows it to transition between different delay configurations. Instead of being locked into fixed 1/4th or 1/5th divisions, the system can dynamically reconfigure its delay elements to achieve various delay values while maintaining calibration accuracy through automated adjustment mechanisms.
Solution Approach 2:
The system enables continuous variation of delay parameters beyond fixed divisions. By allowing the delay value to be dynamically changed based on operational requirements, the system achieves both calibration accuracy and flexibility in selecting different delay values such as 1/3rd, 1/6th, or custom fractions of the clock period.
3Device complexity
If delay lines use fixed configuration, then the circuit is simple, but the response time to process temperature and voltage variations is limited
Solution Approach 1:
The delay line implements a self-adjusting mechanism that automatically detects and compensates for PTV variations without external control. The system monitors its own performance and self-corrects delay inaccuracies, maintaining reliability and fast response time while adding minimal complexity through integrated sensing and adjustment circuitry.
Data Source
AI summary
In an embodiment, a delay circuit includes a ring oscillator circuit and a counter circuit. The ring oscillator circuit includes a delay chain having delay elements and configured to generate one of more clock cycles of an oscillator clock signal in response to a clock cycle of a clock signal. The counter circuit includes two counters that are configured to store a count state corresponding to a number of clock cycles of the oscillator clock signal during a single clock cycle of the clock signal. A first buffer is configured to store the number of clock cycles of the oscillator clock signal. The delay circuit includes a buffer to store a bit pattern corresponding to a number of delay elements traversed in a partial clock cycle of the oscillator clock signal in response to the clock cycle of the clock signal based on outputs of the plurality of delay elements.