Compact Ring Oscillator for Adaptive Voltage Scaling
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Solution Overview
Problem
Existing programmable integrated circuits face challenges in efficiently determining the lowest power supply voltage that supports desired speed while minimizing power consumption, as existing techniques are not adaptive enough to account for variations in physical integrated circuits.
Innovation Solution
A compact speed-testing ring oscillator is integrated into the circuit model, utilizing only two lookup table elements and connected to a power management unit, which adjusts the power supply voltage based on speed-testing outputs to maintain operation above a prescribed speed, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing speed-testing techniques are used to determine operating voltage, then speed testing can be performed, but the device complexity and area consumption increase significantly
Solution Approach 1:
The speed-testing ring oscillator is segmented into discrete configurable logic elements (LUTs) and interconnect resources that are distributed throughout the FPGA fabric. This segmentation allows the oscillator to be built using existing programmable resources rather than requiring a dedicated complex oscillator circuit, thereby reducing overall device complexity while maintaining speed testing capability
Solution Approach 2:
The configurable logic elements and interconnect resources used to build the speed-testing ring oscillator are the same resources used for implementing user logic functions. This universality allows the oscillator to share hardware resources with the main circuit functionality, eliminating the need for separate dedicated testing hardware and reducing device complexity
2Measurement precision
If a speed-testing ring oscillator is added to test circuit speed, then speed measurement is enabled, but the circuit area increases
Solution Approach 1:
The speed-testing ring oscillator utilizes the same configurable logic elements (LUTs) and interconnect resources that are already present and necessary for implementing user logic functions. By making these resources serve dual purposes (both user logic and speed testing), no additional area is required beyond what is already allocated for the main circuit functionality
Solution Approach 2:
The speed-testing ring oscillator is constructed entirely from existing programmable resources within the FPGA fabric itself, without requiring external testing equipment or additional dedicated testing circuitry. The oscillator uses the device's own logic elements and interconnect to perform self-testing, eliminating the need for external area-consuming testing infrastructure
3Use of energy by moving object
If power supply voltage is reduced to minimize power consumption, then energy efficiency improves, but the operating speed decreases
Solution Approach 1:
The power management unit continuously monitors the output frequency of the speed-testing ring oscillator and uses this feedback to dynamically adjust the power supply voltage. When the oscillator frequency indicates that the circuit is operating above the minimum required speed, the power management unit reduces the voltage to minimize power consumption. This closed-loop feedback mechanism enables automatic optimization of the power-speed tradeoff
Solution Approach 2:
The power supply voltage is made dynamic rather than static, allowing it to be adjusted in real-time based on actual circuit performance. The power management unit can change voltage levels during operation to match the actual speed requirements, enabling the circuit to consume minimal power when high speed is not needed while maintaining the ability to increase voltage when higher speeds are required
Data Source
AI summary
Techniques for adaptively scaling power supply voltage of a programmable integrated circuit. Compact speed-testing ring oscillators are inserted into a pre-constructed circuit model to test the speed of speed-critical aspects of the interconnect fabric of the programmable integrated circuit. The speed-testing ring oscillators are compact due to including only two elements configured from lookup table elements (“LUTs”) of the programmable integrated circuit. The speed-testing ring oscillators are connected to a power management unit which receives speed values output from the speed-testing ring oscillators and adjusts the power supply voltage to maintain the speed-testing ring oscillators operating at or above a prescribed speed. If all speed-testing ring oscillators are operating too fast, then power management unit reduces voltage to reduce the total power consumed by the programmable integrated circuit while still maintaining operation above a desired speed.