Dual-Path Ring PLL Frequency Control for Low Phase Jitter
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Solution Overview
Problem
Purely digital PLLs have high phase jitter due to quantized phase error correction, while purely analog PLLs have complex correction paths and large footprints, and hybrid LC tank PLLs are costly and large, making them unsuitable for all applications.
Innovation Solution
A hybrid ring PLL circuit with a digital path and an analog path that simultaneously control the frequency of a ring oscillator, using a digital phase detector and a linear phase detector to provide proportional frequency correction, reducing phase jitter while maintaining a smaller footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a purely digital PLL is used, then the device complexity and footprint are reduced, but the phase jitter increases due to quantized phase error correction
Solution Approach 1:
The patent combines digital and analog correction paths in a hybrid PLL architecture. The digital path provides coarse frequency correction with low complexity, while the analog path provides fine phase adjustment with continuous control, eliminating quantization effects and reducing phase jitter without requiring a fully analog implementation.
Solution Approach 2:
The correction function is segmented into two distinct paths: a digital path for integer frequency division and an analog path for fractional phase adjustment. This segmentation allows each path to operate in its optimal regime, with the digital path handling large-scale frequency changes and the analog path handling precise phase alignment.
2Reliability
If a purely analog PLL is used, then the phase jitter is reduced due to continuous phase error correction, but the device complexity and footprint increase
Solution Approach 1:
The patent merges the advantages of both digital and analog PLLs by implementing a hybrid architecture where the digital path handles frequency locking with simple digital logic, while the analog path handles phase locking with continuous control, achieving low jitter without the full complexity of a traditional analog PLL.
3Reliability
If a hybrid LC tank PLL is used, then the phase jitter is reduced, but the device footprint and cost increase
Solution Approach 1:
The patent replaces the traditional LC tank resonator with a ring oscillator-based frequency synthesizer. This substitution eliminates the need for large-area inductors and capacitors while maintaining the ability to achieve low phase jitter through the hybrid digital-analog correction architecture.
Solution Approach 2:
The patent changes the fundamental operating parameters by using a ring oscillator with digitally controlled delay elements instead of an LC tank. This allows frequency control through digital timing adjustments rather than analog resonant frequency tuning, reducing area while enabling precise frequency synthesis.
Data Source
AI summary
A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.