Reference-Injection Ring PLL Realignment for Low Phase Noise
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Solution Overview
Problem
Phase locked loops (PLL) employing ring type voltage controlled oscillators (VCOs) face significant challenges in reducing phase noise, which degrades system performance due to thermal and flicker noise accumulation, making them unsuitable for various applications despite their lower cost compared to crystal oscillators.
Innovation Solution
A fractional reference-injection phase locked loop (FRIPLL) system is introduced, which includes a ring VCO, a fractional interpolative frequency divider (FIFD), and an oscillator control circuit that generates a realignment signal to align the ring VCO output with a reference clock signal, reducing phase noise by stopping and restarting the ring VCO oscillations at the reference clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a ring VCO is used instead of a crystal oscillator, then cost and power consumption are reduced, but phase noise increases due to thermal and flicker noise accumulation
Solution Approach 1:
The patent applies periodic action by using a gate signal to periodically enable and disable the ring VCO oscillations. The VCO is enabled during the low state of the gate signal and disabled during the high state, creating periodic oscillation intervals that prevent continuous noise accumulation while maintaining cost-effective ring VCO architecture
Solution Approach 2:
The patent implements feedback by using a fractional interpolative frequency divider to divide the VCO output frequency, comparing it with a reference clock signal, and generating a gate signal that feeds back to control the VCO enabling. This closed-loop feedback mechanism ensures the VCO operates only when needed and maintains synchronization with the reference clock, reducing phase noise while keeping power consumption low
2Stability of the object's composition
If the VCO is continuously enabled to maintain frequency, then frequency stability is improved, but phase noise accumulates over many cycles
Solution Approach 1:
The patent uses periodic action by gating the VCO to oscillate only during specific intervals (low state of gate signal) rather than continuously. This periodic operation maintains frequency stability within each active interval while preventing phase noise accumulation over extended periods, as the VCO is periodically reset and realigned with the reference clock
Solution Approach 2:
The patent applies preliminary action by pre-generating the gate signal based on the reference clock and fractional division requirements before controlling the VCO. The gate signal is prepared in advance to enable the VCO at the correct timing, ensuring frequency stability is maintained while preventing phase noise accumulation through proactive control
Data Source
AI summary
Methods and apparatuses are described to reduce phase noise in a low noise fractional reference-injection phase locked loop (FRIPLL). The FRIPLL includes a ring voltage controlled oscillator (VCO). An output of the ring VCO is input to a fractional interpolative frequency divider (FIFD). A signal comparison circuit receives a reference clock signal and a further delayed output of the FIFD. The signal comparison circuit produces a control voltage signal in response to a phase difference between the reference clock signal and the further delayed output of the FIFD. The control voltage signal is input to the ring VCO to control a ring VCO frequency. An oscillator control circuit has a first input and a second input. The first input is a first delayed output of the FIFD. The second input is the reference clock signal. The oscillator control circuit generates a realignment signal which is used to realign a state transition in a ring VCO output signal to the reference clock signal when the ring VCO output signal is in a low state. Realignment occurs repeatedly at a frequency of the reference clock signal.