Injection-Pulsed Ring PLL for Low-Noise High-Frequency Clocks
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Solution Overview
Problem
Conventional phase lock loops (PLLs) for high-frequency operations, such as those exceeding 16 GHz, consume significant power and semiconductor die area, making them impractical for widespread use as local PLLs on a semiconductor die due to size and power distribution limitations.
Innovation Solution
A phase lock loop with injection pulse control is implemented, utilizing a global reference clock signal to suppress phase noise in ring PLLs, which includes a lock-loop circuit with an oscillator, frequency detector, and regulator, allowing for low power and low phase noise operation by injecting pulses based on the global reference clock signal to reduce phase noise in oscillators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LC PLLs are used for high-frequency operation, then phase noise is reduced, but power consumption and die area increase significantly
Solution Approach 1:
The invention divides the PLL system into two functional parts: a shared reference PLL that generates the reference clock signal with low phase noise, and multiple ring PLLs that generate local clock signals. The reference PLL is segmented from the individual communication block PLLs, allowing the expensive low-noise reference generation to be shared across multiple blocks, thereby reducing per-block power consumption while maintaining phase noise performance.
Solution Approach 2:
The reference PLL serves multiple communication blocks simultaneously by providing a shared reference clock signal. This multi-functional approach allows a single low-power reference PLL to support numerous transceivers and communication blocks, eliminating the need for each block to have its own full-featured LC PLL, thus reducing overall power consumption and die area.
2Reliability
If conventional LC PLLs are used for high-frequency operation, then phase noise is reduced, but die area increases significantly
Solution Approach 1:
The PLL functionality is segmented into a shared reference PLL and distributed ring PLLs. The reference PLL, which requires larger area for low phase noise performance, is separated from the communication blocks and shared across them. Each communication block only needs a compact ring PLL, significantly reducing the area per block while maintaining overall phase noise performance through the shared reference.
Solution Approach 2:
Multiple communication blocks share a common reference PLL, merging the reference generation function across multiple blocks. This consolidation eliminates redundant reference PLL instances, reducing total die area while maintaining the low phase noise characteristics needed for high-frequency operation across all shared blocks.
3Use of energy by stationary object
If ring PLLs are used instead of LC PLLs, then power consumption is reduced, but phase noise increases
Solution Approach 1:
The reference PLL acts as an intermediary between the low-power ring PLLs and the phase noise performance requirement. The reference PLL generates a clean reference clock signal that is fed to the ring PLLs, effectively mediating the phase noise issue. This allows the ring PLLs to operate at low power while still achieving low phase noise in their output through the influence of the clean reference signal.
Solution Approach 2:
The invention uses periodic pulse injection from the reference PLL to the ring PLLs at the reference clock frequency. This periodic action synchronizes the ring PLLs to the clean reference signal, effectively transferring the low phase noise characteristics from the reference PLL to the ring PLL outputs without requiring the ring PLLs to consume high power like LC PLLs would.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables reliable operation at high frequencies with reduced phase noise and power consumption, making it suitable for widespread use on semiconductor dies by leveraging a global reference clock to suppress noise in ring PLLs, thereby addressing the size and power constraints of conventional LC PLLs.
Implementation Method 1
The reference clock signal is coupled to the oscillator to suppress noise in the oscillator by pulse injection
Data Source
AI summary
An apparatus comprises a lock-loop circuit including an oscillator, a frequency detector, a charge pump, and a regulator. The regulator is coupled to provide a regulated signal to the oscillator to control frequency. The oscillator and the frequency detector are coupled to receive a reference clock signal. The reference clock signal is coupled to the oscillator to suppress noise in the oscillator by pulse injection. The frequency detector is coupled to receive an oscillator output from the oscillator.