Ring Structure Priority Queues Memory Cache Eviction

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Solution Overview

Problem

Existing caching systems consume significant processing bandwidth due to repeated traversal and evaluation of data blocks for eviction, which reduces efficiency and performance.

Innovation Solution

Implementing a ring structure with rotating priority queues, where data blocks are evicted from the lowest priority queue and moved to higher queues based on access heat values, and maintaining associations between processing engines and queues to reduce unnecessary data movement and improve cache performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If repeated traversal and evaluation of all data blocks is performed for eviction, then cache eviction can be performed, but processing bandwidth is consumed significantly

Engineering Contradiction:
Improvecache eviction correctnessVSAvoidprocessing bandwidth
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the cache into multiple priority queues (first priority queue, second priority queue, etc.) based on access patterns. By dividing the cache evaluation into segmented priority levels, the system avoids traversing all data blocks uniformly, instead focusing evaluation on specific priority queues, thereby reducing overall processing bandwidth consumption while maintaining eviction correctness.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by treating different data blocks with different evaluation intensities based on their priority. High-priority blocks in the first priority queue receive focused evaluation and protection from eviction, while lower-priority blocks in subsequent queues undergo less intensive evaluation. This localized differential treatment reduces total processing bandwidth while ensuring important blocks are preserved.

Inventive Principle:
Principle #3Local quality

2Productivity

If data blocks are moved frequently between queues based on access, then cache performance can be optimized, but redundant data movements increase processing overhead

Engineering Contradiction:
Improvecache performanceVSAvoidprocessing overhead
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent implements dynamic priority queue assignment where data blocks can transition between priority queues based on access patterns. The system dynamically adjusts which queue a block belongs to, allowing hot blocks to move to higher priority queues and cold blocks to lower priority queues. This dynamic reorganization optimizes cache performance by placing frequently accessed blocks in faster-access queues while minimizing unnecessary movements through threshold-based transitions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the priority parameter of data blocks based on access frequency and recency. By modifying the priority level parameter rather than physically moving all blocks frequently, the system optimizes cache performance through parameter adjustment. Blocks only undergo physical movement when priority thresholds are crossed, reducing redundant data movements and associated processing overhead.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11080206B2Ring structure of priority queues for memory cache
Publication Date: 2021.08.03 HEWLETT PACKARD ENTERPRISE DEV LP
  • US11080206B2 patent drawing
  • US11080206B2 patent drawing
  • US11080206B2 patent drawing

AI summary

A computer implemented method includes: storing identifiers of cached data blocks stored in a ring structure comprising a plurality of queues, where each queue is assigned a different priority level based on a base pointer, and where the plurality of queues includes a subset of queues associated with an insertion range of priority levels; during a plurality of partial rotations of the ring structure, inserting new identifiers of data blocks associated with a plurality of processing engines into the subset of queues, where each partial rotation shifts the base pointer to a next higher queue; and maintaining, for multiple partial rotations, an association between a first processing engine and a first queue of the subset of queues until the first queue is shifted out of the insertion range of priority levels.