Ring-Shaped Memory Array Structure Reducing RC Delay
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Solution Overview
Problem
High element density in memory devices leads to increased RC delay and reduced reliability due to reduced pattern width and space, and conventional manufacturing processes are complex and costly, requiring multiple photo/etch steps including pattern cutting.
Innovation Solution
A memory array structure featuring a ring-shaped electrical pattern with word lines, arrays, and contact points, manufactured using a double patterning process without the need for pattern cutting, which reduces manufacturing costs and RC delay by eliminating additional processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If element density is increased to meet small size and large memory capacity requirements, then memory capacity and integration are improved, but RC delay increases and reliability degrades
Solution Approach 1:
The patent applies curvature by designing ring-shaped word lines instead of conventional straight lines. This curved topology allows signals to be transmitted from both ends of the ring simultaneously toward the center, effectively halving the maximum signal propagation distance and reducing RC delay while maintaining high element density
2Quantity of substance
If pattern width is reduced to increase element density, then integration is improved, but resistance increases causing RC delay
Solution Approach 1:
The ring-shaped configuration reduces the maximum distance from any point in the array to a contact point, thereby reducing the effective resistance and capacitance path length even when pattern width is reduced for higher density
Solution Approach 2:
The ring topology transforms the one-dimensional linear signal path into a two-dimensional circular path with multiple access points, allowing simultaneous signal injection from both ends and reducing the effective path length for RC delay
3Manufacturing precision
If conventional manufacturing process with multiple photo/etch steps is used, then manufacturing precision is achieved, but device complexity and cost increase
Solution Approach 1:
The patent merges the formation of ring-shaped patterns and the definition of array regions into a single photo/etch process by using a unified mask pattern that simultaneously creates both features, thereby reducing the total number of process steps
Solution Approach 2:
The mask pattern serves multiple functions: it defines the ring-shaped word lines, establishes the array boundaries, and creates the necessary spacing all in one step, making the process universally applicable for forming complex two-dimensional patterns
Data Source
AI summary
A memory array structure is provided. The memory array structure comprises a ring-shaped electrical pattern comprising a plurality of word lines, an array area comprising a first array, a second array and a plurality of bit lines, and a contact area comprising a plurality of contact points. The first array comprises one part of the word lines, and a first ground select line and a first string select line disposed on both sides of the word lines. The second array comprises another part of the word lines, and a second ground select line and a second string select line disposed on both sides of the word lines. The bit lines are disposed on the first array and the second array, and cross both of the first array and the second array. The word lines electrically contact with an external circuit through the contact points.