Ring-Shaped Stress Buffer Layer for Semiconductor Pad

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Solution Overview

Problem

Modern semiconductor devices face stress-related issues due to the use of low-k materials and copper interconnect posts, which lead to residual stress and failure modes like delamination or cracking, particularly in flip-chip packaging and wafer-level chip scale packaging.

Innovation Solution

The implementation of ring-shaped stress buffer layers formed over metal pads in semiconductor devices, which are specifically designed to reduce residual stress by localizing thicker stress buffers to bump regions, thereby minimizing compressive or tensile loads on the silicon substrate, and can be used in conjunction with copper posts or solder bumps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stress or pressure

If polyimide stress buffer layer is used to reduce stress at low-k dielectric layer, then stress buffer effect is improved, but device reliability deteriorates due to high-temperature curing process causing volume shrinkage and residual stress

Engineering Contradiction:
Improvestress buffer effectVSAvoiddevice reliability
Core Design Contradiction:
Stress or pressureVSReliability

Solution Approach 1:

The stress buffer layer is segmented into a ring-shaped structure with an opening that exposes the metal pad, rather than covering the entire pad area. This segmentation allows the stress buffer to reduce stress in the dielectric layer while minimizing interference with the bonding process and reducing residual stress on the silicon substrate.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The stress buffer layer is applied locally in a ring shape around the metal pad rather than uniformly across the entire bonding area. This local application provides stress buffering where needed (in the dielectric layer) while avoiding areas where it would cause problems (the metal pad bonding region).

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If copper interconnect post technology is used, then finer pitch and higher frequency performance are achieved, but stress on the device increases compared to solder bump

Engineering Contradiction:
Improvepitch precisionVSAvoiddevice stress
Core Design Contradiction:
Manufacturing precisionVSStress or pressure

Solution Approach 1:

The stress buffer layer acts as an intermediary between the copper interconnect post and the low-k dielectric layer. It mediates the stress interaction, absorbing and distributing the higher stress induced by copper posts to protect the dielectric layer from stress-related failures.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Stress or pressure

If polyimide layer is applied for stress buffering, then stress reduction is achieved, but manufacturing complexity increases due to high-temperature and long-time curing process

Engineering Contradiction:
Improveresidual stressVSAvoidcuring process complexity
Core Design Contradiction:
Stress or pressureVSDevice complexity

Solution Approach 1:

The ring-shaped stress buffer layer provides partial coverage compared to a full polyimide layer, which allows stress buffering functionality while reducing the total material volume and associated curing complexity. The opening in the ring reduces the cured material volume and simplifies the process.

Inventive Principle:
Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces residual stress and enhances the reliability of semiconductor devices by localizing stress buffers to specific regions, preventing unnecessary stress loading on the silicon substrate and improving thermal mismatch tolerance.

Implementation Method 1

The implementation of ring-shaped stress buffer layers formed over metal pads in semiconductor devices, which are specifically designed to reduce residual stress by localizing thicker stress buffers to bump regions, thereby minimizing compressive or tensile loads on the silicon substrate

Methodology Applied
Scientific EffectStress buffer: Stress Relaxation

Implementation Method 2

The physical stresses in WLCSP and related flip-chip packages depend upon a combination of several factors, such as device size, architecture, and operating conditions, as well as the actual package design and materials of construction

Methodology Applied
Scientific EffectThermal mismatch: Thermal Expansion

Data Source

PatentUS8283781B2Semiconductor device having pad structure with stress buffer layer
Publication Date: 2012.10.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8283781B2 patent drawing
  • US8283781B2 patent drawing
  • US8283781B2 patent drawing

AI summary

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.