Ring-Shaped Substrate for IC Package Warpage Reduction

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Solution Overview

Problem

The semiconductor industry faces challenges in achieving high integration density and small footprint packaging due to coefficient of thermal expansion (CTE) mismatch and warpage issues in existing packaging technologies, particularly in Package-on-Package (PoP) systems.

Innovation Solution

A ring-shaped substrate with a conductive core and vias is used, which provides mechanical support and reduces warpage by matching CTE with the encapsulant, allowing for a more compact package structure. This substrate is encapsulated with a molding compound and integrated with redistribution structures to form a package component that minimizes CTE mismatch and stacking height.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If traditional substrate packaging is used, then mechanical support is provided, but coefficient of thermal expansion (CTE) mismatch and warpage issues occur

Engineering Contradiction:
Improvemechanical supportVSAvoidCTE mismatch and warpage
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The patent extracts the CTE-matching function from the substrate and assigns it to a dedicated CTE-matching layer. This layer is positioned between the substrate and the encapsulant, specifically designed to bridge the CTE difference between these two components, thereby resolving the warpage issue while preserving the substrate's mechanical support role

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent employs a composite structure consisting of multiple layers with different CTE properties: the substrate, the CTE-matching layer, and the encapsulant. Each layer is selected or designed with specific CTE characteristics to create a gradient that accommodates thermal expansion differences, preventing warpage while maintaining overall structural integrity

Inventive Principle:
Principle #40Composite materials

2Productivity

If Package-on-Package (PoP) technology is used, then integration density and component density are enhanced, but stacking height increases

Engineering Contradiction:
Improveintegration density and component densityVSAvoidstacking height
Core Design Contradiction:
ProductivityVSLength of stationary object

Solution Approach 1:

The patent introduces a ring-shaped substrate configuration that utilizes lateral spatial arrangement instead of purely vertical stacking. The ring structure allows components to be positioned around the perimeter, effectively using the horizontal plane to increase integration density without proportionally increasing the vertical stacking height

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If ring-shaped substrate is used, then warpage is reduced and stacking height is decreased, but manufacturing complexity increases

Engineering Contradiction:
Improvewarpage reductionVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the CTE-matching function into a separate dedicated layer rather than attempting to achieve CTE matching through the entire substrate structure. This segmentation allows each layer to be optimized independently: the substrate for mechanical support, the CTE-matching layer for thermal expansion compatibility, and the encapsulant for protection

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces package warpage and overall height while maintaining mechanical support, enhancing integration density and component density in semiconductor devices.

Implementation Method 1

By avoiding coefficient of thermal expansion (CTE) mismatch between the encapsulant and other components of the package, warpage may be reduced

Methodology Applied
Scientific EffectCoefficient of thermal expansion (CTE) matching: Thermal Expansion

Data Source

PatentUS11527474B2Integrated circuit package and method
Publication Date: 2022.12.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11527474B2 patent drawing
  • US11527474B2 patent drawing
  • US11527474B2 patent drawing

AI summary

In an embodiment, a package includes: a first redistribution structure; a first integrated circuit die connected to the first redistribution structure; a ring-shaped substrate surrounding the first integrated circuit die, the ring-shaped substrate connected to the first redistribution structure, the ring-shaped substrate including a core and conductive vias extending through the core; a encapsulant surrounding the ring-shaped substrate and the first integrated circuit die, the encapsulant extending through the ring-shaped substrate; and a second redistribution structure on the encapsulant, the second redistribution structure connected to the first redistribution structure through the conductive vias of the ring-shaped substrate.