Ring-Trench Capacitor Structure for High-Density DRAM
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Solution Overview
Problem
Traditional three-dimensional DRAM manufacturing processes result in lower DRAM density due to larger layer heights, making it difficult to meet the requirements of modern circuit design, which necessitates the development of non-planar structures like silicon on insulator (SOI), dual-gate, multi-gate, nanowire field effect transistors, and three-dimensional DRAM structures.
Innovation Solution
A memory cell structure with a ring-trench capacitor structure is introduced, where the capacitor structure covers the outer side of the active region and word line structure, reducing the occupied area and height, and using an indium gallium zinc oxide (IGZO) layer for the active region to enhance current driving capability and reduce leakage current, allowing for a more compact and efficient memory cell design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional three-dimensional DRAM manufacturing processes are used, then multiple layers of DRAM can be stacked, but the layer height becomes larger resulting in lower DRAM density
Solution Approach 1:
The patent transitions from conventional planar capacitor structures to a ring-trench capacitor structure that utilizes vertical and radial dimensions. The capacitor is formed by etching a ring-shaped trench around the active region and filling it with conductive material, creating a three-dimensional structure that increases capacitance without increasing planar area or layer height significantly.
Solution Approach 2:
The ring-trench capacitor structure is nested around the active region, with the capacitor trench encircling the channel region. This nested configuration allows the capacitor to be integrated within the same vertical space as the transistor, maximizing space utilization and reducing overall cell area while maintaining low layer height.
2Adaptability or versatility
If non-planar structures like SOI, dual-gate, multi-gate, nanowire FETs are adopted, then circuit design requirements can be met, but device complexity increases
Solution Approach 1:
The device is segmented into distinct functional regions: the active region with channel and connection terminals, the ring-trench capacitor structure, and the insulating dielectric layer. This segmentation allows each component to be optimized independently while maintaining overall simplicity and manufacturability.
Solution Approach 2:
The patent applies different materials and structures to different regions: IGZO material for the active region to enhance current driving capability, ring-trench structure for the capacitor to maximize capacitance density, and insulating dielectric material strategically placed to provide electrical isolation where needed. This localized optimization achieves high performance without requiring complex global restructuring.
Data Source
AI summary
Provided are a memory cell structure, a memory array structure, a semiconductor structure and a manufacturing method thereof. The memory cell structure includes: a substrate, an active region, a word line structure, an insulating dielectric layer, and a capacitor structure. The substrate has a bit line structure therein, and the active region is positioned on the bit line structure. In a direction perpendicular to the substrate, the active region includes a first connection terminal, a second connection terminal away from the first connection terminal, and a channel region positioned between the first connection terminal and the second connection terminal. In the direction perpendicular to the substrate, the word line structure covers a sidewall of the channel region. The insulating dielectric layer covers an outer side of the word line structure, an outer side of the first connection terminal, and an outer side of the second connection terminal.