Ring VCO Buffer Topology for Accurate Multi-Phase Clocks
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Solution Overview
Problem
Conventional ring voltage control oscillators in phase locked loops suffer from high power consumption, large area occupation, and low speed due to the need for multiple stages, which affects the accuracy of multi-phase clock generation and data recovery in communication systems.
Innovation Solution
A ring voltage control oscillator design featuring four-stage delay units and multistage isolation buffer units, where each delay unit outputs two-phase clock signals, reducing the number of stages and power consumption while maintaining high-speed operation through a fully differential structure and symmetrical layout to minimize parasitic delays and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of stages in the delay unit is increased to generate more phases, then the number of output phases is improved, but the power consumption increases proportionally
Solution Approach 1:
The patent combines the delay function and buffer function into a single integrated stage structure. Each stage simultaneously provides delay and buffering capabilities, eliminating the need for separate buffer stages. This merging reduces the total number of stages required to achieve a given number of output phases, thereby reducing power consumption while maintaining the same phase multiplication capability.
Solution Approach 2:
The delay unit stages are designed to perform multiple functions: they provide signal delay, signal buffering, and drive capability simultaneously. This multi-functional design means that each stage contributes to both phase generation and signal integrity maintenance, reducing the need for additional dedicated buffer stages and lowering overall power consumption.
2Adaptability or versatility
If the number of stages in the delay unit is increased to generate more phases, then the number of output phases is improved, but the occupied area increases
Solution Approach 1:
The patent merges the delay element and buffer element into a single integrated stage structure. This consolidation reduces the total number of stages needed to achieve a specific phase multiplication factor, thereby reducing the cumulative area occupied by all stages while maintaining the same number of output phases.
Solution Approach 2:
The patent segments the delay and buffer functions into unified stages where each stage handles both functions. This segmentation approach allows for more efficient space utilization compared to having separate delay stages and buffer stages, as the shared functionality reduces redundant circuitry and inter-stage connections.
3Adaptability or versatility
If the number of stages in the delay unit is increased to generate more phases, then the number of output phases is improved, but the operating speed decreases
Solution Approach 1:
The patent combines delay and buffer functions into single stages, reducing the total number of stages required. Fewer stages mean fewer signal transitions and less cumulative delay through multiple stage interfaces, thereby maintaining higher operating speeds while still achieving the desired phase multiplication.
Solution Approach 2:
The integrated buffer functionality within each delay stage acts as an intermediary that strengthens the signal drive capability between stages. This internal buffering ensures that signals maintain their integrity and speed through the chain of stages, preventing speed degradation that would occur with more numerous separate stages.
4Use of energy by moving object
If the number of stages is reduced to lower power consumption, then the power consumption is improved, but the phase difference accuracy deteriorates due to inconsistent parasitic delays
Solution Approach 1:
The patent merges buffer functionality into each delay stage, ensuring that each stage outputs a fully buffered and driven signal. This consistent buffering across all stages standardizes the output characteristics and minimizes variations in parasitic delays, maintaining phase difference accuracy even with fewer stages.
Solution Approach 2:
The patent applies local buffering at each stage output to ensure consistent signal quality and drive capability. This localized quality enhancement ensures that each stage transition has standardized characteristics, reducing cumulative parasitic effects and maintaining accurate phase differences across all output phases.
Data Source
AI summary
A ring voltage control oscillator includes: a conversion unit (100), cascaded multistage delay units (200) and cascaded multistage isolation buffer units (300). The conversion unit (100) receives a voltage signal controlled by the external, converts the voltage signal into a current signal and respectively transmits the current signal to a plurality of delay units (200) and a plurality of isolation buffer units (300). The delay unit (200) comprises two signal input terminals and two signal output terminals; the isolation buffer unit (300) comprises two signal input terminals and two signal output terminals; a first signal input terminal and a second signal input terminal of the isolation buffer unit (300) are correspondingly connected to a first signal output terminal and a second signal output terminal of the same stage of the delay unit (200), respectively; clock signals outputted by first signal output terminals of two adjacent stages of the isolation buffering units (300) have the same phase difference; clock signals outputted by the second signal output terminals of two adjacent stages of the isolation buffering units (300) have the same phase difference.