Ring VCO PLL Dual Charge Pump for Low-Jitter Loop Stability

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Solution Overview

Problem

Conventional ring VCO based PLLs face a strong trade-off between jitter reduction and loop stability, with high-frequency supply noise and phase noise contributing to significant jitter and instability, affecting the performance of components in a GDDR architecture.

Innovation Solution

A pole-zero compensated ring VCO based PLL architecture is introduced, featuring increased decoupling capacitors and source degeneration resistors to suppress noise and introduce compensating zeros, enhancing loop bandwidth and stability without increasing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If conventional ring VCO based PLL architecture is used, then the circuit is simple, but jitter is high due to supply noise and phase noise

Engineering Contradiction:

Improvecircuit architectureVSAvoidjitter performance

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The VCO control path is segmented into two separate paths: an integral path for low-frequency variations and a proportional path for high-frequency supply noise. This segmentation allows each path to be optimized independently for its specific frequency range, improving overall jitter performance without requiring complete redesign of the entire PLL architecture.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A decoupling capacitor is introduced as an intermediary element at the ring VCO node to filter high-frequency noise. Additionally, source degeneration circuits with resistors and capacitors serve as intermediary filtering elements in the proportional path, effectively reducing the impact of supply noise on the VCO without significantly increasing circuit complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If decoupling capacitors are increased to reduce jitter, then jitter performance improves, but loop stability deteriorates

Engineering Contradiction:

Improvejitter performanceVSAvoidloop stability

Core Design Contradiction:

ReliabilityVSStability of the object's composition

Solution Approach 1:

The control path is divided into integral and proportional paths, allowing the decoupling capacitor to be placed specifically in the proportional path for high-frequency noise filtering. This segmentation enables the capacitor to improve jitter performance without adversely affecting the integral path's contribution to loop stability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Source degeneration resistors and capacitors are introduced in the proportional path to modify the frequency response characteristics. These parameter changes create a compensating zero that counteracts the destabilizing effect of large decoupling capacitors, allowing optimal jitter performance while maintaining loop stability.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If source degeneration circuits are added to suppress high-frequency noise, then phase noise is reduced, but device complexity increases

Engineering Contradiction:

Improvephase noiseVSAvoidcircuit architecture

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Source degeneration circuits are applied locally only in the proportional path where high-frequency noise suppression is needed, rather than throughout the entire PLL circuit. This localized application effectively reduces phase noise while minimizing the increase in overall device complexity.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The source degeneration circuits in the proportional path serve multiple functions: they filter high-frequency supply noise, provide additional decoupling, and help stabilize the loop. This multi-functionality reduces the need for separate dedicated noise filtering components, thereby limiting the increase in device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Reliability

If loop bandwidth is increased to reduce jitter, then jitter performance improves, but stability margin decreases

Engineering Contradiction:

Improvejitter performanceVSAvoidstability margin

Core Design Contradiction:

ReliabilityVSStability of the object's composition

Solution Approach 1:

Source degeneration resistors and capacitors are introduced in the proportional path to modify the frequency response characteristics. These parameter changes create a compensating zero that counteracts the destabilizing effect of increased loop bandwidth, allowing optimal jitter performance while maintaining adequate stability margin.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12425032B1Ring voltage controlled oscillator-based phase locked loop with dual charge pump architecture

Publication Date: 2025.09.23 CADENCE DESIGN SYST INC

AI summary

Embodiments included herein are directed towards a ring voltage-controlled oscillator based phase locked loop circuit. Embodiments may include an integral path including a plurality of resistors and a plurality of transistors configured to correct low frequency variations and a proportional path in electrical communication with the integral path, the proportional path including a plurality of transistors and a source degeneration circuit. Embodiments may further include a decoupling capacitor located at a ring voltage-controlled oscillator node in electrical communication with the proportional path, wherein the source degeneration circuit operates to cancel any effect from the ring voltage-controlled oscillator node.