Ringback Circuit Filtering Data Strobe Signal to Prevent Write Post-Ambles
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor memory devices experience write post-amble ringing due to phase differences between the data strobe signal and the system clock signal, leading to potential data glitches and failures, which are not effectively addressed by existing ringback circuits that rely on domain crossing margins and filtering in the clock signal domain.
Innovation Solution
A ringback circuit for semiconductor memory devices that synchronizes a seed signal with the data strobe signal during the pre-amble period to generate filtering control signals, allowing for filtering of the data strobe signal in the data strobe signal domain, eliminating the need for domain crossing margins and supporting various preamble periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If filtering is performed in the clock signal domain using conventional ringback circuits, then the circuit structure is simpler, but write post-amble ringing cannot be effectively prevented due to phase differences between data strobe signal and system clock signal
Solution Approach 1:
The patent inverts the conventional approach by performing filtering in the data strobe signal domain instead of the clock signal domain. The ringback circuit generates a ringback signal synchronized with the data strobe signal DQS, and the filtering unit filters the data strobe signal using this ringback signal. This inversion allows effective prevention of write post-amble ringing by eliminating phase difference issues between clock and data signals.
Solution Approach 2:
The patent introduces a ringback signal as an intermediary element that is synchronized with the data strobe signal DQS. This ringback signal serves as a mediator between the data strobe signal and the filtering operation, enabling accurate timing alignment without requiring domain crossing margins. The ringback signal is generated by synchronizing with DQS and delaying by a predetermined period, acting as a reference for the filtering process.
2Adaptability or versatility
If domain crossing margins are used to synchronize clock and data domains, then timing alignment is achieved, but the circuit cannot accommodate various preamble periods and becomes less adaptable
Solution Approach 1:
The patent implements dynamic adaptability by making the filtering operation dependent on the actual data strobe signal characteristics rather than fixed clock domain timing. The ringback signal is generated by synchronizing with each DQS signal and delaying by a predetermined period, allowing the filtering timing to dynamically adapt to different preamble periods. This eliminates the need for fixed domain crossing margins and enables support for various preamble schemes.
3Measurement precision
If filtering control signals are generated by synchronizing with the clock signal, then the clock domain timing is simplified, but phase differences cause inaccurate filtering of the data strobe signal
Solution Approach 1:
The patent inverts the synchronization approach by generating filtering control signals from the data strobe signal domain instead of the clock signal domain. The ringback signal is created by synchronizing with DQS and delaying, then this ringback signal directly controls the filtering operation. This inversion ensures that the filtering control signals are inherently synchronized with the data strobe signal, eliminating phase difference issues and achieving accurate filtering.
Data Source
AI summary
A circuit for a semiconductor memory device includes: a filtering control signal generation unit configured to synchronize a seed signal activated in a pre-amble period of a data strobe signal with the data strobe signal and sequentially generate a plurality of filtering control signals in response to the seed signal; and a filtering signal output unit configured to generate a filtering signal for filtering the data strobe signal in response to the plurality of filtering control signals and a plurality of burst length (BL) control signals.