Ripple Adder Timing With Alternating Inverted Carry Signals
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Solution Overview
Problem
Traditional ripple carry adders are too slow for modern applications due to their linearly increasing worst-case propagation delay with the number of precision bits, and they waste silicon area and energy, while conventional carry look-ahead arithmetic is overkill for devices requiring low precision.
Innovation Solution
A logic circuit with alternating binary number systems and reduced delay elements, where at least one carry output is inverted relative to the carry input, and clock signals are successively delayed to match the processing delay interval, eliminating the need for additional inverting functions in carry circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional ripple carry adder is used, then device complexity is reduced, but processing speed deteriorates due to linearly increasing propagation delay
Solution Approach 1:
The patent inverts the carry output signal at alternating bit positions (odd positions) to eliminate the need for additional inverting logic gates. By using an alternating binary number system where odd-position bits are naturally inverted, the carry propagation path is simplified, reducing the processing delay by 40-50% while maintaining adder circuit functionality.
2Speed
If conventional carry look-ahead arithmetic is used, then processing speed is improved, but device complexity and silicon area increase
Solution Approach 1:
The patent applies local quality by implementing inversion only at specific odd-position bit locations rather than uniformly across all bits. This localized approach allows the circuit to achieve speed improvements similar to carry look-ahead arithmetic while maintaining the simplicity of ripple carry structure, as the inversion is applied selectively where needed in the alternating binary system.
3Measurement precision
If additional inverting functions are added to carry circuits, then processing accuracy is improved, but processing delay increases
Solution Approach 1:
The patent converts the potential harm of signal inversion (which would normally add delay) into a benefit by utilizing the alternating binary number system. The natural inversion property of odd-position bits in this system eliminates the need for separate inverting gates, thereby maintaining carry propagation accuracy while reducing processing delay by 40-50%.
4Measurement precision
If more precision bits are added, then measurement precision is improved, but processing delay increases linearly
Solution Approach 1:
The patent applies inversion at alternating bit positions throughout the entire precision range. This approach allows the addition of more precision bits while maintaining constant-speed performance, as each alternating bit position independently processes carries without accumulating delay, effectively breaking the linear relationship between precision bits and propagation delay.
Data Source
AI summary
Apparatus and method to logically process signals representative of multiple-bit numbers include successively delaying applications of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input registers that is substantially equal to the processing delay interval per bit-level of the logical processing stage. In this way, successively more significant bits of each of plural numbers being logically processed are validly available for processing at each bit-level logic stage after a delay. At least one of the bit-representative signals is inverted prior to the input registers or prior to processing by the logical processing stage. The delay is reduced by omitting an inverting function in a carry circuit associated with at least one logical processing stage. Similarly, output registers for latching the logic output of each bit-level logic stage are clocked at successively delayed intervals substantially equal to the processing delay interval.