Ripple-Counter Delay Line for Low-Power Pulse Filtering
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Solution Overview
Problem
Existing programmable delay lines using synchronous counters face challenges in balancing speed, area, and power consumption, and struggle to achieve desired delays without compromising on pulse filtering and duty cycle adjustments.
Innovation Solution
A programmable delay line is implemented using a ripple counter and an oscillator, where the counter counts clock cycles from a programmed offset value, generating a signal to transition and invert the output signal, with a control circuit to enable and disable the oscillator, and an enable circuit to manage clock cycles based on input and output signal differences, allowing for fine delay adjustments and pulse filtering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a synchronous counter is used to ensure simultaneous transition of all counter output bits, then timing margin for the compare function is improved, but power consumption increases and area usage increases
Solution Approach 1:
The counter is divided into multiple independent ripple-carry stages, where each stage transitions sequentially rather than simultaneously. This segmentation allows each bit to be processed independently with minimal power consumption while maintaining the required timing characteristics through the ripple effect.
Solution Approach 2:
Instead of using a synchronous counter that transitions all bits simultaneously (conventional approach), the patent inverts the approach by using an asynchronous ripple counter where bits transition sequentially. This inversion resolves the contradiction by achieving acceptable timing margins without the high power consumption of simultaneous transitions.
2Measurement precision
If the counter width is increased to achieve the desired delay, then delay precision is improved, but area usage increases
Solution Approach 1:
The patent extends the delay capability from a single counter width dimension to multiple dimensions by using multiple ripple counters in parallel or cascaded configurations. This allows achieving greater delay precision without proportionally increasing the area of a single counter, as the delay is distributed across multiple smaller counter units.
Solution Approach 2:
Multiple ripple counters are nested or cascaded together to achieve the desired total delay. Each counter contributes a portion of the total delay, and they are arranged in a hierarchical structure where the output of one counter feeds into the next, achieving extended delay precision with compact area usage.
3Area of stationary object
If a fast counter is used to minimize oscillator area, then area is reduced, but power consumption increases
Solution Approach 1:
The counter operates in a dynamic ripple mode where each stage activates only when the previous stage transitions, rather than all stages operating continuously at high speed. This dynamic operation reduces power consumption while maintaining the ability to achieve the required counting speed for the delay function, allowing smaller oscillator area without the penalty of high power consumption.
Data Source
AI summary
A programmable delay line includes a first oscillator that is enabled and generates a plurality of clock cycles of a clock signal in response to a transition of the input signal. A first programmable ripple counter is coupled to the first oscillator, counts with each successive clock cycle to a programmed count, and generates a first signal in response to reaching the programmed count. A control circuit is coupled to the first oscillator and to the first programmable ripple counter. The control circuit transitions the output signal and disables the first oscillator in response to the first signal.