Ripple Counter Sampling with Adjustable Clock Delay Matching
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Solution Overview
Problem
Sampling digital signals from a binary ripple counter becomes challenging at high operating speeds due to skew among output bits, leading to mismatched delays between the clock and data paths, which affects the accuracy of sampling, especially for more significant bits.
Innovation Solution
The use of adjustable clock delay elements, where the delay of clock signals is adjusted based on the output bits of the binary ripple counter, ensuring correct sampling by setting specific delay relationships between clock and data paths, thereby compensating for potential mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fixed delay elements are used in the sampling clock path, then the device complexity is reduced, but the sampling accuracy deteriorates at high operating speeds due to delay mismatches between clock and data paths
Solution Approach 1:
The patent applies dynamics by making the delay elements adjustable rather than fixed. The sampling controller dynamically adjusts the delay of clock signals CK1, CK2, etc. based on feedback from the output bits D0, D1, etc. This allows the system to adapt to varying operating conditions and maintain accurate sampling at high speeds by compensating for delay mismatches between the clock path and data path.
Solution Approach 2:
The patent implements feedback by using the output bits from the binary ripple counter to control the adjustable delay elements in the sampling clock path. The output bits provide information about the actual delay experienced in the data path, which is then used to adjust the clock path delays to achieve matching, thereby improving sampling accuracy.
2Productivity
If the operating speed is increased, then the productivity is improved, but the sampling accuracy deteriorates due to accumulated delay mismatches in more significant bits
Solution Approach 1:
The patent enables the sampling system to operate at high speeds by dynamically adjusting the clock delays based on the actual delay experienced by the data bits. This dynamic adjustment compensates for accumulated delay mismatches that would otherwise degrade sampling accuracy at high operating speeds.
Solution Approach 2:
The patent changes the delay parameter of the clock signals dynamically based on the operating conditions and the actual delay in the data path. By adjusting the delay parameter of CK1, CK2, etc., the system maintains accurate sampling even at high operating speeds where fixed delays would result in significant errors.
3Measurement precision
If adjustable clock delay elements are used to match data delays, then the sampling accuracy is improved, but the device complexity increases due to additional control circuitry
Solution Approach 1:
The patent applies self-service by having the sampling controller automatically adjust its own clock delays based on feedback from the output bits. The system uses its own output to control its internal delay elements, eliminating the need for external calibration or complex control circuitry. The adjustable delay elements are controlled by the output bits themselves, creating a self-regulating system.
4Measurement precision
If the counter length is increased, then the measurement range is improved, but the sampling accuracy deteriorates due to greater accumulation of delay mismatches
Solution Approach 1:
The patent compensates for delay accumulation in long counters by dynamically changing the delay parameters of the clock signals based on feedback from the output bits. This allows the system to maintain accurate sampling across multiple count stages even when the counter length is increased to expand the measurement range.
Data Source
AI summary
The output bits of a binary ripple counter are used to control the sampling of those output bits, thereby ensuring accurate sampling. A sampler is provided with adjustable delay elements that permit accurate sampling regardless of: delay mismatch between the sampler and a data path of the counter; the length of the counter; operating speed; or PVT variations.