Consecutive Register Selection in RISC Processors
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Solution Overview
Problem
Reduced instruction set computing (RISC) processors face challenges in efficiently specifying multiple registers due to limited bit-width, making it difficult to implement instructions like 'push' and 'pop' operations, as there are not enough bits to indicate the operator and the registers to be affected within the short instruction length.
Innovation Solution
A method that reads and interprets two operands in a reduced instruction set to select a set of consecutive registers, allowing for efficient 'push' and 'pop' operations by specifying the starting register and the number of registers to be selected, thereby reducing the number of bits required and enabling the selection of a larger number of registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a bitmap instruction is used to specify multiple registers, then multiple registers can be identified in one instruction, but the instruction cannot be implemented in reduced instruction sets with short instructions due to insufficient bits
Solution Approach 1:
The register selection mechanism is segmented into two parts: a base register specifier and a count specifier. This segmentation allows the instruction to be divided into manageable bit fields that fit within reduced instruction width constraints while still enabling selection of multiple consecutive registers through the combination of base register index and register count parameters.
Solution Approach 2:
The patent transitions from a one-dimensional bitmap approach (where each bit represents a register) to a two-dimensional approach using base register index and register count. This dimensional change allows efficient encoding of consecutive register ranges without requiring a full bitmap, thus reducing instruction width while maintaining the ability to specify multiple registers.
2Length of moving object
If a lookup table is used to specify register combinations, then multiple registers can be identified using fewer bits, but only common register combinations can be specified
Solution Approach 1:
The register selection mechanism is made dynamic by allowing the count specifier to vary, enabling the instruction to adapt to different register range sizes as needed. This dynamic approach replaces the static lookup table with a flexible calculation-based method that can handle any consecutive register range, not just pre-defined common combinations.
Solution Approach 2:
The patent changes the parameters used for register selection from discrete lookup table indices to a combination of base register index and count. This parameter change enables continuous variation in the number and position of registers selected, providing flexibility for both common and uncommon register combinations while maintaining compact instruction encoding.
Data Source
AI summary
A method of executing an instruction set to select a set of registers, includes reading a first instruction of the instruction set; interpreting a first operand of the first instruction to represent a first register S to be selected; interpreting a second operand of the first instruction to represent a number N of registers to be selected; and selecting N consecutive registers starting at the first register S to form the set of registers.