RISC Floating-Point Stack Emulation via Pointer Modulo
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Solution Overview
Problem
Current virtual machines face inefficiencies and compatibility issues when emulating the floating-point stack mechanism of X86 processors on RISC processors, particularly due to the lack of a similar architecture, which hinders binary translation and performance.
Innovation Solution
A RISC processor device with a floating-point register file, decoding section, and control register that emulates a floating-point register stack operation by using a pointer register and pointer operation module to simulate the stack operations of an X86 processor, allowing for the emulation of stack push and pop operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing virtual machines emulate X86 floating-point stack mechanism on RISC processors, then compatibility with X86 software is improved, but execution efficiency deteriorates due to tremendous architectural differences and high overhead
Solution Approach 1:
The patent creates a virtual X86 floating-point stack by copying the stack mechanism concept into the RISC processor environment. It uses a pointer register to simulate the top-of-stack pointer and a modulo function to emulate the circular buffer behavior of X86's 8-stack-register architecture, achieving software-level compatibility without hardware duplication
Solution Approach 2:
The patent introduces a decoding section as an intermediary between the RISC instruction set and the emulated X86 floating-point operations. This decoder translates RISC instructions into equivalent X86 stack operations, mediating the architectural differences and enabling seamless software execution across incompatible platforms
2Adaptability or versatility
If a floating-point register stack is provided in CISC processor for floating-point operations, then floating-point operation capability is improved, but device complexity increases compared to RISC processors without such stack
Solution Approach 1:
The patent makes the RISC processor's floating-point unit universal by enabling it to perform both native RISC floating-point operations and emulated X86 stack-based operations. The same floating-point register file serves dual purposes: direct RISC access and X86 stack simulation via the pointer register, eliminating the need for separate hardware stacks
Solution Approach 2:
The patent introduces dynamic register mapping where the effective floating-point register indices are determined at runtime based on the pointer register value and modulo operation. This dynamic behavior allows the static RISC register file to exhibit the dynamic stack-pointer-dependent access patterns characteristic of X86 architecture
Data Source
AI summary
A Reduced Instruction Set Computing (RISC) processor is capable of emulating operation of a floating-point register stack. The RISC processor may include a floating-point register file containing a plurality of floating-point registers, a decoding section for decoding operation instructions, and a floating-point operation section. The RISC processor may also include a control register for controlling status of floating-point registers, and for controlling the decoding section and the floating-point operation section, to thereby emulate a floating-point register stack using the floating-point register file. The decoding section may include a pointer register for maintaining a stack operation pointer, and for storing a value of the stack operation pointer. The floating-point operation section may also include a pointer operation module for operating the pointer register, for emulating stack operation of the stack pointer of the pointer register, and for modifying and monitoring the stack pointer during emulation of floating-point register stack.