RISC Processor Prefix Instruction Operator Reinterpretation
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Solution Overview
Problem
Reduced instruction set computing (RISC) processors with 16-bit instructions are limited by a restricted number of bits for expressing operators, which restricts the number of available operators, limiting the complexity of instructions that can be expressed.
Innovation Solution
A method and processor architecture that utilize a prefix instruction to reinterpret operator fields in associated instructions, allowing a single operator field to represent different operators based on the presence of a prefix, thereby increasing the number of operators available for use in each instruction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 16-bit instruction size is used, then code size is reduced, but the number of available operators is restricted
Solution Approach 1:
The operator field in the instruction is designed to serve multiple functions: it can represent different operators depending on the context provided by the preceding instruction. This multi-functionality allows the same bit field to encode various operations (arithmetic, logical, data movement) without requiring additional bits, thereby maintaining compact instruction size while expanding operator versatility.
Solution Approach 2:
A prefix instruction acts as an intermediary between the instruction format and the operator field. This prefix modifies the interpretation of the operator field, enabling the same operator field to represent different operators based on the prefix context. This intermediary mechanism resolves the contradiction by allowing contextual reinterpretation without increasing instruction size.
2Adaptability or versatility
If instruction size is increased to 32-bits, then more operators are available, but code size increases
Solution Approach 1:
The instruction stream is segmented into a prefix instruction followed by a main instruction. The prefix contains context information that modifies the interpretation of the main instruction's operator field. This segmentation allows the system to achieve 32-bit instruction functionality in a distributed manner across two 16-bit instructions, maintaining code size efficiency while expanding operator availability.
Solution Approach 2:
The solution adds a temporal dimension to instruction interpretation by using a preceding instruction to modify the meaning of the current instruction's operator field. Instead of increasing the spatial dimension (instruction width), the system uses the time dimension (sequence of instructions) to encode additional operational meaning, thereby expanding operator availability without increasing code size.
Data Source
AI summary
A method of executing an instruction set having a first instruction and a second instruction, includes: reading the first instruction; determining whether the first instruction is integral with the second instruction; reading the second instruction; when the first instruction is integral with the second instruction, interpreting a first operator field of the second instruction to represent a first operator; and when the first instruction is not integral with the second instruction, interpreting the first operator field of the second instruction to represent a second operator, wherein the first operator is different to the second operator.