RISC-V APLIC-IMSIC Lost Interrupt Detection

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Solution Overview

Problem

Modern processors with multi-level interrupt systems often fail to detect and manage 'lost interrupt events,' where subsequent interrupts for the same target are not captured, which can be critical in safety-related contexts like automotive applications.

Innovation Solution

The proposed solution extends APLIC and IMSIC interrupt identities with lost interrupt detection mechanisms and information structures, allowing for the detection, consolidation, and notification of lost interrupt events to processing cores.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multi-level interrupt systems are implemented to handle multiple interrupt sources with different priorities, then interrupt handling capability and system responsiveness are improved, but the system may fail to detect lost interrupt events, reducing reliability

Engineering Contradiction:

Improveinterrupt handling capabilityVSAvoiddetectability of lost interrupt events

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent implements feedback mechanisms by having the interrupt controller send interrupt lost information back to the computing core. When an interrupt event is lost (detected when an interrupt arrives while the interrupt pending bit is already set), the controller sets an interrupt lost bit and transmits this information to the core, enabling the core to detect and respond to lost interrupts appropriately.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent introduces an intermediary mechanism (the interrupt lost detection and reporting system) between the interrupt controller and the computing core. This intermediary detects lost interrupt events and communicates them to the core, bridging the gap between the controller's internal state and the core's awareness of interrupt events.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If interrupt lost detection mechanisms are added to the interrupt system, then reliability and detectability of lost events are improved, but device complexity increases

Engineering Contradiction:

Improvedetectability of lost interrupt eventsVSAvoidcomplexity of interrupt system

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the interrupt lost detection functionality with the existing interrupt controller structure. The interrupt lost bit is integrated into the same register structure as the interrupt pending bit, and the detection logic is combined with the existing interrupt handling logic, rather than adding completely separate detection hardware.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The interrupt controller is enhanced to perform multiple functions: it continues to handle normal interrupt events while also detecting and reporting lost interrupt events. The same interrupt controller infrastructure serves both traditional interrupt handling and lost event detection, reducing the need for additional dedicated components.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250165278A1Consolidation of interrupt lost events in multi-level interrupt system

Publication Date: 2025.05.22 INFINEON TECHNOLOGIES AG

AI summary

Systems, methods, and circuitries are provided for detecting lost interrupt events in a reduced instruction set computer-V (RISC-V) architecture. An example architecture includes an advanced platform level interrupt controller (APLIC) and an incoming message signaled interrupt (MSI) controller (IMSIC) coupled to the APLIC. The APLIC includes a plurality of respective vectors connected to respective external interrupt inputs, wherein each vector is mapped to an interrupt priority and each vector comprises a vector interrupt lost (IL) bit. The IMSIC is configured to receive MSI from the APLIC and to maintain an interrupt file that includes a set of a set of interrupt lost (IL) bits indexed by interrupt priority.