RISC-V Trusted Execution Emulation for ARM TrustZone Compatibility
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Solution Overview
Problem
Software programs are crafted differently for various processor architectures due to distinct instruction sets and hardware characteristics, necessitating platform-specific optimizations and creating challenges for cross-architecture compatibility and security feature emulation.
Innovation Solution
A RISC-V processor is modified to emulate security features like ARM TrustZone by using physical memory protection (PMP) to create isolated computing environments, employing a secure transaction identifier bit and microarchitecture optimizations such as adding a SWID column to the TLB and utilizing a configuration status register to ensure secure and regular worlds have distinct address spaces and privileges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If software is customized for different processor architectures, then performance and resource utilization are optimized, but cross-architecture compatibility and ease of deployment deteriorate
Solution Approach 1:
The patent copies the ARM TrustZone security architecture model into the RISC-V processor by emulating equivalent security mechanisms. Instead of requiring software to be rewritten for RISC-V, the system creates a virtual TrustZone environment that replicates the secure world/normal world separation, allowing ARM-optimized software to run on RISC-V hardware with minimal modifications.
Solution Approach 2:
The RISC-V processor is enhanced with multi-functional security features that can emulate different architecture-specific security models. The unified security management unit can operate in multiple modes to support both native RISC-V security mechanisms and emulated ARM TrustZone functionality, making the processor universally compatible with software designed for different architectures.
2Reliability
If architecture-specific security features are implemented, then security protection is enhanced, but device complexity and implementation difficulty increase
Solution Approach 1:
The patent introduces an intermediary security management unit that sits between the core RISC-V processor and the emulated TrustZone interface. This intermediary layer handles the complexity of translating ARM TrustZone security concepts into RISC-V native security mechanisms, shielding the rest of the system from implementation complexity while maintaining strong security protection.
Solution Approach 2:
The system dynamically changes security parameters and configuration states to emulate different security architectures. By modifying runtime parameters such as security mode flags, address space identifiers, and privilege levels, the processor can switch between native and emulated security models without requiring hardware redesign, thus managing complexity through software-configurable parameters.
3Reliability
If security isolation mechanisms are added, then security world separation is improved, but address space management and transaction overhead increase
Solution Approach 1:
The patent merges the security isolation mechanisms with the existing RISC-V memory management unit (MMU) and address translation logic. Instead of adding separate isolation hardware, the security world separation is integrated into the address translation process, where secure and non-secure address spaces are managed through unified page table structures and translation lookaside buffers (TLBs), reducing overall system complexity.
Solution Approach 2:
The system adds a new dimension to address space management by introducing security attributes as an additional layer in the address translation hierarchy. Security world identifiers and permission bits are embedded within existing address structures, allowing security isolation to be enforced alongside standard virtual-to-physical address translation without requiring separate management mechanisms.
Data Source
AI summary
Computer-implemented methods and associated hardware for static trusted execution environment for inter-architecture processor program compatibility are disclosed herein. A device (e.g., a Reduced Instruction Set Computing-Five (RISC-V) device), may emulate a static trusted execution environment (e.g., ARM TrustZone) using physical memory protection (PMP). A regular world may have access to only a portion of an address space of the device, while a secure world may have access to the full address space. A secure world identifier (SWID) may be stored in a configuration status register (CSR) only accessible by a mode (e.g., machine mode). When an entry is added to a translation lookaside buffer (TLB), the SWID may be added as part of a tag to differentiate secure world entries from regular world entries.