3D Interconnected Multi-Core Processor Architecture for RISC-V Performance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing RISC-V architectures face limitations in meeting high-performance processor requirements due to inefficiencies in core connectivity and data interaction, particularly in traditional design fields with stringent CPU performance demands.
Innovation Solution
A 3D interconnected multi-core processor architecture is designed with a main control layer, micro core array layer, and accelerator layer, featuring cooperative main cores, efficient data interaction, and a 3DRouter for optimized data transmission, enabling faster processing and improved performance by distributing complex instructions across micro cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional RISC-V architecture is used, then simplicity and open source advantages are maintained, but processing performance for high-demand applications is insufficient
Solution Approach 1:
The processor architecture is segmented into three distinct layers: main control layer with main cores, micro core array layer with multiple micro cores, and accelerator layer. This segmentation allows each layer to specialize in specific functions, improving overall processing performance while maintaining manageable complexity through modular design.
Solution Approach 2:
The patent introduces a vertical three-dimensional layered architecture rather than traditional planar layouts. By organizing cores and functional units across multiple vertical layers (main control layer, micro core array layer, accelerator layer), the system achieves higher integration density and improved data interaction pathways without proportionally increasing horizontal complexity.
2Speed
If core connectivity is strengthened to improve processing efficiency, then data interaction speed increases, but system complexity increases
Solution Approach 1:
A 3D router is introduced as an intermediary component to manage data interaction between different layers and cores. The 3D router simplifies the connectivity complexity by providing a standardized interface for data transmission, enabling fast data interaction between main cores, micro cores, and accelerators without requiring complex direct connections between all components.
3Productivity
If complex instructions are distributed to micro cores for processing, then processing throughput increases, but instruction conversion complexity increases
Solution Approach 1:
The main cores in the main control layer perform preliminary instruction conversion, translating complex instructions into simpler instructions that the micro cores can execute. This preliminary action is performed in advance before instructions are distributed to the micro core array, enabling parallel processing and increasing throughput while centralizing the conversion complexity in the main control layer rather than distributing it throughout the system.
Data Source
AI summary
An RISC-V-based 3D interconnected multi-core processor architecture and a working method thereof. The RISC-V-based 3D interconnected multi-core processor architecture includes a main control layer, a micro core array layer and an accelerator layer, wherein the main control layer includes a plurality of main cores which are RISC-V instruction set CPU cores, the micro core array layer includes a plurality of micro unit groups including a micro core, a data storage unit, an instruction storage unit and a linking controller, wherein the micro core is an RISC-V instruction set CPU core that executes partial functions of the main core; the accelerator layer is configured to optimize a running speed of space utilization for accelerators meeting specific requirements, wherein some main cores in the main control layer perform data interaction with the accelerator layer, the other main cores interact with the micro core array layer.