RISC-V Fast Interrupt Controller Hardware Context Management

The patent introduces a hardware stack pointer register (ssp) and hardware stack management mechanisms as intermediaries between the interrupt controller and the processor core. This hardware intermediary automatically saves and restores caller-save register values during interrupt handling, reducing the instruction overhead while maintaining compatibility with standard RISC-V calling conventions. The hardware stack pointer acts as a mediator that bridges software interrupt handlers and the actual register state management.

The patent replaces the software-based mechanical process of manual register saving and restoring with a hardware-based automatic stack management system. Instead of using software instructions to push and pop register values onto the stack, the hardware automatically performs these operations through dedicated circuitry and control logic, significantly reducing the time and instruction count required for interrupt context management.

The patent segments the interrupt management functionality by introducing separate interrupt controller modules (such as CLIC - Core-Local Interrupt Controller) that operate alongside the centralized PLIC. Each interrupt controller handles specific types of interrupts independently, allowing nested interrupts to be supported by dividing the interrupt management into hierarchical segments. This segmentation enables different privileged modes to have their own interrupt controllers that can nest interrupts independently.

The patent implements nested interrupt capability by allowing interrupt controllers to be nested within each other hierarchically. The CLIC can be nested within the PLIC structure, where the CLIC handles core-local interrupts that can nest within externally triggered interrupts managed by the PLIC. This nested doll structure enables multiple levels of interrupt nesting while maintaining a relatively simple overall architecture.

The patent enables the interrupt controller to perform self-service operations by automatically managing the stack pointer and register state saving/restoring processes. The hardware stack pointer register (ssp) and associated control logic automatically update the stack pointer, save caller-save register values, and restore them upon interrupt return, without requiring complex software intervention. This self-service capability reduces software operation complexity while maintaining nested interrupt functionality.

The patent changes the operational parameters of the interrupt controller by introducing hardware-managed stack pointer registers and automatic context saving/restoring mechanisms. Instead of relying on software to manage stack pointers and register states, the hardware parameters are configured to automatically perform these operations, simplifying the software interface while enabling nested interrupts. The parameter change from software-managed to hardware-managed stack operations reduces complexity.

The patent performs preliminary action by pre-configuring hardware stack pointer registers and automatic context management mechanisms before interrupts occur. The hardware is pre-programmed with the necessary logic to automatically save and restore caller-save registers during interrupt handling, eliminating the need for runtime prologue and epilogue instructions. This preliminary hardware configuration ensures calling convention compliance while reducing interrupt handling time.

The patent substitutes the mechanical software-based prologue and epilogue instruction sequences with a hardware-based automatic context management system. Instead of executing multiple software instructions to save and restore registers, the hardware automatically performs these operations through dedicated circuitry, significantly reducing the time required for interrupt handling while maintaining compliance with RISC-V calling conventions.