RISC-V Interrupt System Context Saving Optimization
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Solution Overview
Problem
The existing RISC-V interrupt processing mechanisms, such as CLIC, face inefficiencies in saving context registers like mcause and mepc, and have slow interrupt response times, especially during non-vectored interrupt processing and tail biting scenarios, which hinder the speed of jumping to the interrupt subroutine entry.
Innovation Solution
The introduction of new CSR registers like pushmcause and pushmepc, along with optimized instructions like csrrwi, mintsel_jal, and jalmnxti, allows for direct stacking and updating of mcause and mepc values, reducing the number of instructions required and accelerating the interrupt response by enabling faster context saving and jumping to the interrupt subroutine.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional RISC-V interrupt processing mechanisms (CLIC) are used to save context registers, then the interrupt processing mechanism is established, but the saving speed of mcause and mepc is slow and requires multiple instructions
Solution Approach 1:
The patent combines the saving of mcause and mepc registers with the interrupt service routine entry jump operation into a single unified process. By merging these operations, the system eliminates separate save steps and achieves faster context saving while maintaining all necessary functionality.
Solution Approach 2:
The patent pre-configures the interrupt service routine entry addresses in the mtvec register before interrupts occur. This preliminary preparation allows the system to directly jump to the correct ISR entry without needing to calculate or search for addresses during the interrupt handling process, significantly reducing the time required for context saving and entry.
2Reliability
If traditional interrupt processing instructions are used, then the interrupt mechanism functions correctly, but the number of instructions required to jump to interrupt subroutine entry is large
Solution Approach 1:
The patent merges multiple sequential operations (saving mcause, saving mepc, jumping to ISR entry) into a single integrated operation. This consolidation maintains the correctness of each individual step while eliminating the overhead of executing them as separate instructions, thereby improving processing efficiency.
Solution Approach 2:
The patent extracts the address calculation and jump logic from the general interrupt handling process by dedicating the mtvec register specifically for storing ISR entry addresses. This extraction allows the system to directly use the pre-stored address without needing additional instructions for address resolution, reducing the instruction count while ensuring correctness.
3Reliability
If conventional context saving methods are used in CLIC mode, then all context information is preserved, but the clock cycles required for saving registers are excessive
Solution Approach 1:
The patent combines the context saving operations with the interrupt service routine invocation into a single atomic operation. By merging these steps, the system ensures that all context information (mcause, mepc) is saved completely while eliminating the time overhead of sequential execution, achieving both reliability and speed.
Solution Approach 2:
The system pre-positions the interrupt service routine addresses in the mtvec register during system initialization or configuration. This preliminary action eliminates the need for runtime address calculation and ensures that context saving can proceed directly to the correct location without delays, reducing clock cycles while maintaining completeness.
Data Source
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AI summary
An interrupt system for RISC-V architecture includes an original register in a CLIC, a pushmcause register, a pushmepc register, an interrupt response register, and an mtvt2 register; the pushmcause register is used to store a value in an mcause on a stack by means of an instruction; the pushmepc register is used to store a value in an mepc on a stack by means of an instruction; the interrupt response register is used to respond to a non-vectored interrupt request issued by a CLIC by means of an instruction, obtain an interrupt subroutine entry address, and modify a global interrupt enable; and the mtvt2 register is used to store a base address of an non-vectored interrupt in a CLIC mode.