RISC-V Parallel Kernel Execution With Context-Based OpenCL Support
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Solution Overview
Problem
Existing parallel processing devices, such as GPUs, lack open access to processor core technology, hindering the development of new technologies using open computing language (OpenCL) programming models.
Innovation Solution
A parallel processing device employing RISC-V cores as processor cores, with a structure that includes execution context data and a method for executing kernels based on this data, allowing for the use of OpenCL programming models.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If commercial GPU with SIMT cores is used for parallel processing, then processing performance is improved, but processor core technology accessibility deteriorates
Solution Approach 1:
The patent segments the processor core technology into open-source RISC-V core components that can be independently accessed and modified, while maintaining the overall GPU architecture for parallel processing. This allows separate optimization of core accessibility without compromising system-wide performance.
Solution Approach 2:
The patent implements a universal processor core design based on RISC-V architecture that can serve multiple functions: executing OpenCL kernels, supporting various parallel processing workloads, and providing a standardized interface for developer access. This multi-functional core replaces proprietary SIMT cores while maintaining compatibility.
2Productivity
If proprietary SIMT core architecture is used, then execution efficiency is improved, but technology development flexibility deteriorates
Solution Approach 1:
The patent implements dynamic configuration capabilities where RISC-V core parameters and execution characteristics can be adjusted during runtime to optimize for different kernel types and workload patterns. This dynamic adaptability maintains execution efficiency while providing flexibility for technology development.
Solution Approach 2:
The patent utilizes parameter changes in the RISC-V core configuration to optimize execution efficiency for different parallel processing scenarios. By adjusting core parameters such as instruction pipeline depth, register allocation, and memory access patterns, the system maintains high performance while benefiting from open-source flexibility.
3Adaptability or versatility
If open-source RISC-V cores are adopted, then technology accessibility is improved, but execution context management complexity increases
Solution Approach 1:
The patent performs preliminary organization of execution context data before kernel execution, structuring all necessary context information in advance. This preliminary action simplifies the runtime management complexity by ensuring that execution contexts are pre-configured and readily available when needed.
Solution Approach 2:
The patent introduces an intermediary layer that manages the complexity of execution context data for RISC-V cores. This intermediary handles the translation and organization of context information, shielding developers from the underlying complexity while maintaining open-source accessibility.
4Adaptability or versatility
If execution context data is structured for RISC-V cores, then OpenCL compatibility is improved, but data transmission overhead increases
Solution Approach 1:
The patent merges execution context data transmission with the kernel launch process, combining multiple data transfer operations into a single unified transmission. This reduces the overall overhead by eliminating redundant transmission steps while maintaining full OpenCL compatibility.
Solution Approach 2:
The patent implements efficient copying mechanisms for execution context data that minimize transmission overhead. By using optimized memory copy operations and leveraging the RISC-V architecture's capabilities, the system reduces data transmission time while ensuring accurate context transfer for OpenCL kernel execution.
Data Source
AI summary
Provided is a parallel processing device with one or more group processors, in which each of the one or more group processors includes a plurality of instance processors configured to process a kernel execution instance for a predetermined parallel program model-based kernel, each of the plurality of instance processors includes a register storing context reference information including an identifier of a group processor to which the instance processor belongs and an identifier of the instance processor, and each of the plurality of instance processors executes the kernel by reading execution context data, which is stored in a memory for execution of the kernel, using the context reference instance.