Rising-Edge Clock Generation Without Complex PLL Circuits
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Solution Overview
Problem
Existing clock generation methods, particularly those using PLL circuits, face challenges in achieving high precision while maintaining a simple structure, especially in systems that operate at a specific edge of the clock signal, as they require complex logic and many transistors, and software-type PLLs struggle to ensure precision.
Innovation Solution
A method that converts an input clock to generate an output clock by setting a desired output clock value and a variable value, determining the rising edge of the input clock, and adjusting the output clock accordingly, allowing for precise clock generation without a complex PLL structure by comparing calculated values with the input clock value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a PLL circuit is used to generate a clock with a certain duty ratio, then the clock precision is improved, but the device complexity increases and more transistors are needed
Solution Approach 1:
The patent extracts only the essential function of clock generation for rising-edge systems, removing the unnecessary duty ratio adjustment functionality of the PLL circuit. This allows the system to achieve sufficient precision without the complex feedback and control mechanisms required for duty ratio management.
Solution Approach 2:
Instead of using a traditional PLL that generates a clock with a specific duty ratio and then adjusting it, the patent inverts the approach by directly generating a clean rising-edge clock signal without duty ratio constraints, eliminating the need for complex adjustment mechanisms.
2Device complexity
If a software-type PLL is used to simplify the structure, then the device complexity is reduced, but the clock precision cannot be ensured
Solution Approach 1:
The patent replaces the software-based clock generation approach with a hardware-based counter and comparator system. This hardware implementation provides deterministic timing and precise edge detection, ensuring clock precision while maintaining structural simplicity through direct digital logic operations.
3Adaptability or versatility
If a PLL circuit is used to adjust the clock for a system needing a certain duty ratio, then the clock generation capability is improved, but the device complexity increases
Solution Approach 1:
The patent extracts only the necessary clock generation function for rising-edge systems, removing the duty ratio adjustment capability that is not needed for such systems. This simplification eliminates complex feedback loops and control mechanisms while maintaining adequate performance for the specific application.
Data Source
AI summary
A method of converting an input clock to generate an output clock and providing a certain system with the output clock is provided. The method includes setting up a desired output clock value and a variable value and determining whether the input clock is the rising edge; adding the output clock value to the variable value to provide a calculated value when the input clock is the rising edge; comparing the calculated value with the input clock value; and outputting, when the calculated value is equal to or larger than the input clock value as a result of comparison, the output clock as logic state ‘1’ and setting, a value obtained by subtracting the input clock value from the calculated value, as the variable value.