RLC Reassembly Timer Adjustment Using a Learning Model
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Solution Overview
Problem
Existing wireless communication networks face challenges in managing reassembly timers, leading to inefficiencies in bandwidth usage and latency due to pre-configured timer settings that are either too long, causing unnecessary delays, or too short, resulting in excessive retransmissions and failures.
Innovation Solution
Implementing dynamic reassembly timer adjustments based on learning model outputs to optimize timer durations and parameters, allowing for real-time adjustments to improve flexibility and accuracy in reassembly operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If pre-configured reassembly timer settings are used, then device complexity is reduced and ease of operation is improved, but bandwidth utilization deteriorates and latency increases due to suboptimal timer durations
Solution Approach 1:
The patent implements dynamic reassembly timer adjustment by introducing a learning model that continuously adapts timer duration based on observed network conditions and segment reception patterns. The timer transitions from a static pre-configured value to a dynamic parameter that is optimized in real-time, resolving the contradiction between ease of operation and latency reduction.
Solution Approach 2:
The system employs feedback mechanisms where the learning model observes segment reception outcomes and uses this information to adjust future timer durations. This closed-loop approach allows the system to automatically optimize timer settings based on actual network performance, reducing latency while maintaining operational simplicity.
2Device complexity
If pre-configured reassembly timer settings are used, then device complexity is reduced, but bandwidth utilization deteriorates due to excessive retransmissions and failures
Solution Approach 1:
The learning model enables the system to self-optimize timer settings by automatically learning from past performance and adjusting timer durations without external intervention. This self-service capability allows the system to reduce bandwidth waste from excessive retransmissions while keeping the overall device architecture relatively simple.
Solution Approach 2:
The patent changes the timer duration parameter dynamically based on learned patterns and observed network conditions. By adjusting this critical parameter rather than redesigning the entire system, the patent achieves improved bandwidth utilization with minimal increase in device complexity.
3Loss of time
If dynamic reassembly timer adjustments are implemented, then latency is reduced and bandwidth utilization is improved, but device complexity increases due to learning model integration
Solution Approach 1:
The patent introduces dynamic timer adjustment through a learning model that adapts timer duration based on observed network conditions. This dynamic approach reduces latency by optimizing timer settings in real-time, accepting a moderate increase in device complexity as the cost of achieving superior performance.
4Reliability
If longer reassembly timer durations are used, then segment reassembly reliability is improved, but latency increases and bandwidth is wasted due to unnecessary delays
Solution Approach 1:
The patent dynamically changes the timer duration parameter based on learned network conditions and segment reception patterns. This allows the system to maintain reliability by extending the timer when needed while reducing latency by shortening it when conditions permit, resolving the contradiction between these two requirements.
Data Source
AI summary
In one aspect, a device for wireless communication is disclosed. The device includes at least one processor and a memory coupled to the at least one processor. The at least one processor is configured to cause the device to: receive reassembly timer configuration information. The at least one processor is also configured to receive one or more radio link control (RLC) segments, each RLC segment associated with a sequence number (SN), wherein the one or more RLC segments are associated with a reassembly timer expiration time based on the reassembly timer configuration information. The at least one processor is further configured to: release, prior to the reassembly timer expiration time, the one or more RLC segments based on an adjusted reassembly timer expiration time. The adjusted reassembly timer expiration time is determined based on an output from a learning model of the device. Other aspects are described and claimed.