RLPC Circuit Double Data Rate NAND Flash Testing
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Solution Overview
Problem
Current probe testing for NAND type integrated circuits, particularly NAND flash memory, faces increased testing times as the density of transistors grows, leading to prolonged loading and unloading times, necessitating a method to enhance testing rates without significant hardware changes.
Innovation Solution
Modifying the test circuit to operate at a double data rate (DDR) using a reduced low pin count (RLPC) interface, which involves a controller, pad logic, pipeline stages, and an RLPC circuit to control data transfer, allowing data to be sent and received on both the rising and falling edges of a clock signal, thereby doubling the data transfer rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If single data rate testing is used with RLPC interface, then hardware complexity is kept minimal, but testing time increases significantly as memory density increases
Solution Approach 1:
The patent changes the data transfer rate parameter from single data rate to double data rate by utilizing both rising and falling edges of the clock signal for data transfer. This parameter change allows the testing system to achieve twice the data transfer rate without changing the fundamental RLPC interface structure or adding significant hardware complexity.
2Loss of time
If double data rate operation is implemented, then testing time is reduced, but hardware modifications are required
Solution Approach 1:
The patent implements dynamic data transfer by utilizing both rising and falling edges of the clock signal, allowing the system to adaptively transfer data at twice the rate. The existing RLPC interface components are made dynamic by enabling them to operate at double data rate through proper timing control, rather than requiring complete hardware redesign.
3Quantity of substance
If transistor density increases in NAND devices, then storage capacity increases, but probe testing time increases proportionally
Solution Approach 1:
The patent changes the data transfer rate parameter to double data rate, which directly addresses the contradiction between increased memory density and reduced testing rate. By transferring data at twice the speed through utilizing both clock edges, the system can maintain acceptable testing rates even as device capacity increases.
Data Source
AI summary
Briefly, in accordance with one or more embodiments, an apparatus to test a semiconductor device comprises a controller configured to perform one or more tests on the semiconductor device, a reduce low pin count (RLPC) circuit configured to write data to the semiconductor device or read data from the semiconductor device at a double data rate (DDR) with respect to a single data rate (SDR), and pad logic to couple to the semiconductor device, the pad logic configured to provide a trimmable data access time from clock (tAC) signal to select different access times of a single data rate (SDR) or a double data rate (DDR) mode of operation, wherein a loading time or an unloading time of the semiconductor device being tested, or a combination thereof, is reduced when a DDR mode is selected.