Replacing Metal Gates and Contacts with Single CMP Isolation
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Solution Overview
Problem
Current methods for forming integrated circuits with fin-type field effect transistors and discrete replacement metal gates and contacts require multiple chemical mechanical polishing processes, leading to gate height loss and potential performance degradation due to the use of high dielectric constant materials.
Innovation Solution
Forming gate cut and contact cut trenches at the same process level and filling them with the same low-K isolation material, allowing for a single chemical mechanical polishing process to minimize gate height loss and process variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate cut and contact cut trenches are formed at different process levels with different filling materials, then electrical isolation is achieved, but multiple CMP processes are required causing gate height loss and increased process variation
Solution Approach 1:
The patent merges the formation of gate cut trenches and contact cut trenches into a single process step, forming both trenches at the same process level and filling them with the same low-K isolation material. This eliminates the need for multiple CMP processes, thereby preventing gate height loss and reducing process variation while still achieving the required electrical isolation between adjacent gates and contacts.
Solution Approach 2:
The patent uses a universal low-K isolation material for both gate cut trenches and contact cut trenches, replacing the traditional approach of using different materials (such as silicon nitride for gate cuts and silicon oxycarbide for contact cuts). This universal material serves multiple functions: providing electrical isolation, maintaining gate height, and enabling a single CMP process, thus simplifying the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces gate height loss and process variation while optimizing device performance by using a low-K isolation material for both trench types, ensuring efficient electrical isolation and improved circuit performance.
Implementation Method 1
filling them with the same low-K isolation material, allowing for a single chemical mechanical polishing process
Implementation Method 2
allowing for a single chemical mechanical polishing process to minimize gate height loss and process variation
Data Source
AI summary
In a method for forming an integrated circuit (IC) structure, which incorporates multiple field effect transistors (FETs) with discrete replacement metal gates (RMGs) and replacement metal contacts (RMCs), gate cut trench(es) and contact cut trench(es) are formed at the same process level. These trench(es) are then filled at the same time with the same isolation material to form gate cut isolation region(s) for electrically isolating adjacent RMGs and contact cut isolation region(s) for electrically isolating adjacent RMCs, respectively. The selected isolation material can be a low-K isolation material for optimal performance. Furthermore, since the same process step is used to fill both types of trenches, only a single chemical mechanical polishing (CMP) process is needed to remove the isolation material from above the gate level, thereby minimizing gate height loss and process variation. Also disclosed herein is an IC structure formed according to the method.