Replacement Metal Gate VTFETs for Precise Channel Length Control
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Solution Overview
Problem
Conventional fabrication techniques for vertical field-effect transistors (FETs) face challenges in scaling due to thermal budget constraints, leading to variations in channel length, threshold voltage shifts, and increased leakage current, which are not adequately addressed by high-temperature processes.
Innovation Solution
The implementation of a replacement metal gate (RMG) process for vertical transport FETs (VTFETs) that allows for accurate channel length definition, self-aligned top junctions, and multiple channel lengths, while avoiding gate-to-source/drain region shorts through the formation of self-aligned contact capping layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-temperature processes are used for conventional FET fabrication, then manufacturing progress can be made, but thermal budget constraints cause variations in channel length, threshold voltage shifts, and increased leakage current
Solution Approach 1:
The gate structure is segmented into multiple functional layers: a dummy gate formed during conventional processing, and a replacement metal gate formed later through selective removal and metal deposition. This segmentation allows different parts of the gate to serve different purposes at different stages, enabling continued use of high-temperature processes while achieving precise final channel length control through the self-aligned nature of the replacement gate formation.
Solution Approach 2:
A dummy gate is formed preliminarily during conventional FET fabrication processes before the actual metal gate is created. This preliminary gate structure enables subsequent self-aligned removal and replacement, allowing the channel length to be precisely defined by the dummy gate dimensions while avoiding thermal damage to already-formed structures. The dummy gate serves as a template that guides the formation of the final metal gate.
2Ease of manufacture
If conventional fabrication techniques are used, then manufacturing can proceed, but variations in channel length and threshold voltage shifts occur due to thermal budget constraints
Solution Approach 1:
The gate formation process is segmented into distinct stages: conventional dummy gate formation, selective removal of the dummy gate in specific regions, and metal gate deposition. This segmentation isolates the sensitive metal gate formation from high-temperature processes, protecting the threshold voltage from thermal-induced shifts while maintaining ease of manufacture by integrating with existing fabrication workflows.
Solution Approach 2:
The dummy gate acts as an intermediary structure that facilitates the formation of the final metal gate. It is formed during conventional processing, then selectively removed to create openings for metal deposition. This intermediary enables the transition from conventional to advanced gate structures without directly exposing the final gate to damaging thermal processes, thereby ensuring threshold voltage stability.
3Productivity
If high-temperature processes are applied, then manufacturing can continue, but leakage current increases due to thermal damage
Solution Approach 1:
Source and drain regions are formed preliminarily before the metal gate is deposited, using the self-aligned dummy gate as a reference. This preliminary formation allows subsequent low-temperature metal gate deposition without re-exposing sensitive regions to high-temperature processing, thereby preventing thermal-induced leakage current while maintaining manufacturing continuity.
Solution Approach 2:
The self-aligned contact capping layer acts as an intermediary protective structure formed over the metal gate contact regions. It prevents direct exposure of these sensitive areas to potential thermal damage during subsequent processing steps, thereby reducing leakage current generation while allowing manufacturing to proceed without interruption.
Data Source
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AI summary
A method of forming a semiconductor structure comprises forming a plurality of fins disposed over a top surface of a substrate and forming one or more vertical transport field-effect transistors (VTFETs) from the plurality of fins using a replacement metal gate (RMG) process. A gate surrounding at least one fin of a given one of the VTFETs comprises a gate self-aligned contact (SAC) capping layer disposed over a gate contact metal layer, the gate contact metal layer being disposed adjacent an end of the at least one fin.