RMII Ethernet PHY Clock Phase Alignment
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Solution Overview
Problem
In 100 Mb RMII Ethernet physical layer devices, there is a significant uncertainty in transmit latency due to the lack of a known relationship between the 50 MHz reference clock and the 125 MHz transmit clock, resulting in a minimum 20 ns uncertainty in data transmission latency.
Innovation Solution
A system and method that modifies the transmit operation by resetting the divide-by-five circuit to align the 125 MHz transmit clock with the optimal phase for data transfer, allowing consistent phase alignment for all subsequent packets, thereby reducing latency uncertainty.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the 50 MHz reference clock is used to initiate data transfer without phase alignment mechanism, then the interface protocol is simple, but the transmit latency uncertainty increases to 20 ns
Solution Approach 1:
The patent applies preliminary action by establishing phase alignment between the 50 MHz reference clock and the 125 MHz transmit clock before data transmission begins. The system performs clock phase alignment in advance, ensuring that the transmit clock is synchronized with the reference clock phase, thereby eliminating latency uncertainty without adding complexity to the data transfer protocol itself.
2Device complexity
If no phase alignment between reference clock and transmit clock is implemented, then the device complexity is low, but the transmit latency uncertainty is 20 ns
Solution Approach 1:
The patent implements feedback by continuously monitoring the phase relationship between the 50 MHz reference clock and the 125 MHz transmit clock, and adjusting the transmit clock phase based on detected phase differences. This feedback mechanism ensures that the transmit clock remains aligned with the reference clock phase, eliminating latency uncertainty while maintaining manageable device complexity through automated phase synchronization.
3Ease of operation
If the transmit clock phase is randomly determined without alignment, then the system operation is simple, but the latency varies by up to 20 ns depending on clock phase relationship
Solution Approach 1:
The patent applies preliminary action by establishing phase alignment between the 50 MHz reference clock and the 125 MHz transmit clock before data transmission begins. The system performs clock phase alignment in advance, ensuring that the transmit clock is synchronized with the reference clock phase, thereby eliminating latency uncertainty without adding complexity to the data transfer protocol itself.
Data Source
AI summary
A system and method for minimizing transmit latency uncertainty in a 100 Mb RMII Ethernet physical layer device is disclosed. A 100 Mb RMII Ethernet transmit physical layer device comprises a divide circuit that selects a phase of a transmit clock signal for transmitting data. The invention comprises a reset circuit that aligns the divide circuit to select an optimal phase of the transmit clock signal for transmitting data. The reset circuit of the invention is capable of reducing the transmit latency uncertainty from approximately twenty nanoseconds to four nanoseconds.