Low Power Random Number Source Using Ring Oscillator Phase Noise
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Solution Overview
Problem
Portable military communication equipment requires cryptographic quality random number sources that consume low power, as ring oscillators used in previous solutions draw large amounts of power, especially in high-rate CMOS applications.
Innovation Solution
A random number source utilizing a ring oscillator to generate an internal clock signal with random phase noise, connected to first and second linear feedback shift registers, which accumulate entropy to produce true random numbers while minimizing power consumption. The size of the registers can be varied to trade off entropy for power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a plurality of ring oscillators are used to generate true random numbers, then cryptographic quality randomness is achieved, but power consumption increases significantly
Solution Approach 1:
The patent extracts only the essential random phase noise component from the ring oscillator output, rather than using multiple ring oscillators. The single ring oscillator's phase jitter is captured and processed through linear feedback shift registers to generate cryptographically secure random numbers, eliminating the need for multiple oscillators and their associated power consumption.
Solution Approach 2:
The patent replaces the mechanical/hardware-intensive approach of using multiple parallel ring oscillators with a more efficient system using linear feedback shift registers (LFSRs) processed in the digital domain. This substitution reduces power consumption while maintaining cryptographic quality through the accumulation of phase noise entropy over multiple clock cycles.
2Reliability
If larger linear feedback shift registers are used, then entropy of random output increases, but power consumption increases
Solution Approach 1:
The patent employs dynamic adjustment of the LFSR size based on the required entropy output rate. The system can adaptively select between different register configurations (e.g., 32-bit, 64-bit, or 128-bit registers) depending on the cryptographic application requirements, allowing optimization between entropy quality and power consumption in real-time operation.
Solution Approach 2:
The patent accumulates entropy over multiple clock cycles by processing partial outputs from the ring oscillator through the LFSR. Rather than requiring a single large register, the system uses smaller registers that are iteratively updated, accumulating sufficient entropy for cryptographic use while minimizing the power required by any single register stage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution generates true random numbers with low power consumption, reducing the power requirements compared to traditional ring oscillator-based systems, while maintaining cryptographic quality randomness.
Implementation Method 1
The random phase noise in the internal clock signal may be based upon a phase jitter between the internal clock signal and the system clock signal
Data Source
AI summary
A random number source includes a ring oscillator generating an internal clock signal having random phase noise, and a first linear feedback shift register connected to the ring oscillator. A counter is connected to a first tap of the first linear feedback shift register for generating a count signal. A feedback bit controller is connected to a second tap of the first linear feedback shift register for generating a random feedback bit for a time based upon the count signal. A second linear feedback shift register is connected to the feedback bit controller for generating a random number based upon the random feedback bit.