Random Number Generator Test Circuit Fault Detection
Solution Overview
Problem
Existing random number generators and their test circuits face challenges in achieving higher entropy and efficiency, particularly in detecting faults and ensuring the reliability of generated random bits.
Innovation Solution
A test circuit for random number generators is designed to detect faults in series of random bits by using at least one test unit that verifies the number of bits generated without detecting a second fault, compared to a threshold inversely related to the probability of fault occurrence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional test circuits are used to detect faults in random number generators, then fault detection capability is provided, but the complexity of the test circuit increases and entropy evaluation becomes insufficient
Solution Approach 1:
The test circuit is divided into multiple independent test units, each responsible for specific fault detection tasks. This segmentation allows the complex verification process to be distributed across simpler modular components, reducing overall circuit complexity while maintaining comprehensive fault detection capability.
Solution Approach 2:
A counter unit is introduced as an intermediary component that tracks the number of random bits generated between fault detections. This mediator enables the system to evaluate entropy by counting bits without requiring complex direct analysis, simplifying the overall test circuit architecture.
2Reliability
If multiple test units are added to detect different faults, then fault detection coverage is improved, but the device complexity increases
Solution Approach 1:
Each test unit is designed with multi-functionality to detect multiple types of faults using similar computational approaches. The test units can identify various fault patterns including successive identical bits, sum threshold violations, and other statistical anomalies, reducing the need for separate dedicated test circuits for each fault type.
Solution Approach 2:
The test circuit evaluates different parameters of random bit sequences (such as succession of identical bits, sum of bits in windows, frequency distributions) to detect various faults. By changing the parameters being monitored rather than adding purely structural test components, the system achieves comprehensive fault detection with controlled complexity.
3Measurement precision
If the threshold for fault detection is set to be very sensitive, then detection precision is improved, but false positive rate increases reducing productivity
Solution Approach 1:
The test circuit incorporates feedback mechanisms where the results of fault detection and entropy evaluation are fed back to adjust the verification process. When entropy is sufficient, the system can operate with higher thresholds to maintain productivity; when entropy drops, sensitivity increases to detect faults earlier, optimizing the balance between precision and throughput dynamically.
Solution Approach 2:
The verification threshold and sensitivity of the test circuit are made dynamic rather than fixed. The system adapts its detection sensitivity based on the evaluated entropy level of the random number generator, allowing high precision when needed while maintaining high productivity when the generator is operating normally with sufficient entropy.
Data Source
Figure 1~2
Figure 3
AI summary
This description relates to a 1. Test circuit (202) of a random number generator adapted to provide a series of random bits (Random) and comprising at least one test unit (201) configured to detect a fault in the series of random bits (Random), said test circuit (202) being adapted to verify whether, after the detection of a first fault by the test unit (201), the number of random bits, generated by the random number generator without detection of a second fault by the test unit (201), is less than a first threshold.