RNIC FPGA Virtualization for NVMe Data Redundancy
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Solution Overview
Problem
Conventional information processing systems lack efficient methods for data redundancy and high availability, especially when using Just a Bunch of Flash (JBOF) with Non-Volatile Memory express (NVMe), as they do not effectively utilize storage resources to manage data replication and high throughput communication.
Innovation Solution
A processing method that virtualizes a Field Programmable Gate Array (FPGA) into Dynamic Random Access Memory (DRAM) to replicate or split data into packets, reporting virtual memory addresses to a Remote-direct-memory-access-enable Network Interface Controller (RNIC), allowing data to be transmitted efficiently over a fabric channel to NVMe controllers without CPU or OS involvement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional information processing systems allocate SSDs to computing servers without dedicated hardware for data replication, then storage resources are underutilized and hardware costs increase, but system complexity and latency are reduced
Solution Approach 1:
The RNIC is designed to perform multiple functions: it acts as a network interface controller for fabric channel communication, a memory controller for managing DRAM storage, and a data replication engine for creating redundant copies. This multi-functionality allows a single device to handle storage, networking, and data protection tasks that would traditionally require separate hardware components, thereby improving storage resource utilization without proportionally increasing system complexity
Solution Approach 2:
The system implements self-service data replication where the RNIC automatically performs data packet replication and distribution to multiple NVMe controllers without requiring external intervention or additional dedicated replication hardware. The FPGA virtualization enables the RNIC to autonomously manage memory allocation and data routing, allowing the storage system to serve itself for data redundancy operations
2Speed
If data is transmitted via fabric channel with NVMe over Fabric, then throughput and latency performance are improved, but compatibility with conventional systems decreases
Solution Approach 1:
The RNIC acts as an intermediary device that bridges the high-speed NVMe over Fabric protocol with conventional storage systems. It receives data packets from the fabric channel at high speed, processes them through virtualized memory spaces, and distributes them to NVMe controllers that interface with standard SSDs. This intermediary approach enables the system to achieve low-latency fabric channel performance while maintaining compatibility with conventional storage hardware and protocols
3Productivity
If FPGA is virtualized into DRAM for data packet replication, then data redundancy efficiency is improved, but memory resource management complexity increases
Solution Approach 1:
The FPGA is dynamically virtualized into DRAM memory spaces that can be reconfigured based on workload requirements. The RNIC can create multiple virtual memory instances from a single physical DRAM pool, dynamically allocating memory resources to different data replication tasks as needed. This dynamic virtualization approach improves data replication efficiency by allowing flexible resource allocation while the underlying DRAM hardware remains unchanged, managing complexity through software-controlled memory mapping rather than physical reconfiguration
Data Source
AI summary
A processing method of data redundancy is utilized for a Non-Volatile Memory express (NVMe) to transfer data via a fabric channel from a host terminal to a Remote-direct-memory-access-enable Network Interface Controller (RNIC) and a Just a Bunch of Flash (JBOF). The processing method comprises virtualizing a Field Programmable Gate Array (FPGA) of the RNIC into a Dynamic Random Access Memory (DRAM) and storing the data to the DRAM; replicating or splitting the data into a plurality of data packets and reporting a plurality of virtual memory addresses corresponding to the plurality of data packets to the RNIC by the FPGA; and reading and transmitting the plurality of data packets to a plurality of corresponding NVMe controllers according to the plurality of virtual memory addresses; wherein the FPGA reports to the RNIC that a memory size of the FPGA is larger than that of the DRAM.