RNS MAC Accelerator Architecture for Low-Power CNN Convolution
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Solution Overview
Problem
Deep convolutional neural networks (DCNNs) face challenges in efficiently processing large datasets due to high computational requirements, particularly in real-time applications like mobile and embedded platforms where storage and power consumption are limited, and existing number systems like binary and floating-point systems suffer from carry propagation issues and complex operations.
Innovation Solution
The implementation of a hardware architecture for convolutional neural networks (CNNs) using Residue Number Systems (RNS) at low precision, with Multiply-And-Accumulate (MAC) units performing convolutions in the residue domain and dedicated converters for binary-to-residue and residue-to-binary conversions, leveraging properties like periodicity and delayed modulo reduction to optimize area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If binary or floating-point systems are used for DCNN computations, then computational accuracy is maintained, but carry propagation issues and complex operations increase area and power consumption
Solution Approach 1:
The patent transforms the number system parameters from binary or floating-point to Residue Number System (RNS). This parameter change fundamentally alters how computations are performed: RNS represents numbers as tuples of residues modulo different integers, enabling carry-free addition and multiplication. The MAC units operate directly in the residue domain, performing modulo operations instead of standard arithmetic, which eliminates carry propagation chains and reduces hardware complexity while maintaining computational accuracy for DCNN operations
Solution Approach 2:
The patent substitutes the traditional binary/floating-point arithmetic mechanism with RNS-based modulo arithmetic mechanism. Instead of using complex binary adders and multipliers that require carry propagation logic, the system uses simpler modulo arithmetic units that operate independently on each residue component. This mechanical substitution replaces complex sequential carry propagation with parallel modulo operations, significantly reducing area and power consumption
2Device complexity
If RNS is used for low-precision convolutions, then area and power consumption are reduced, but overflow and rounding errors are introduced
Solution Approach 1:
The patent implements delayed modulo reduction as a form of beforehand cushioning. Instead of performing modulo operations at every intermediate step (which would accumulate rounding errors), the system accumulates computations in the residue domain and applies modulo reduction only at critical points or at the end of computation stages. This approach cushions against error accumulation by maintaining higher precision longer in the residue domain, then periodically reducing modulo to keep values within representable ranges
Solution Approach 2:
The patent employs feedback mechanisms through the converter units that transform between binary and RNS domains. The binary-to-residue converter prepares input data by computing residues modulo the RNS moduli set, and the residue-to-binary converter reconstructs final results from residue tuples. These feedback conversion mechanisms ensure that data maintains accuracy across domain transformations, and the system can detect and correct overflow conditions by monitoring residue values against modulus boundaries
3Measurement precision
If DCNN processes large quantities of data adaptively, then learning accuracy is improved, but computational requirements and processing time increase
Solution Approach 1:
The patent segments the DCNN computation into distinct functional blocks: binary-to-residue converter units, multiple parallel MAC hardware accelerator clusters operating in the residue domain, and residue-to-binary converter units. Each cluster processes different feature maps or filter sets independently. This segmentation enables parallel processing of multiple data streams simultaneously, dramatically improving productivity while maintaining the adaptive learning accuracy of the full DCNN through coordinated operation of all segments
Data Source
AI summary
A system includes an addressable memory array, one or more processing cores, and an accelerator framework coupled to the addressable memory. The accelerator framework includes a Multiply ACcumulate (MAC) hardware accelerator cluster. The MAC hardware accelerator cluster has a binary-to-residual converter, which, in operation, converts binary inputs to a residual number system. Converting a binary input to the residual number system includes a reduction modulo 2m and a reduction modulo 2m−1, where m is a positive integer. A plurality of MAC hardware accelerators perform modulo 2m multiply-and-accumulate operations and modulo 2m−1 multiply-and-accumulate operations using the converted binary input. A residual-to-binary converter generates a binary output based on the output of the MAC hardware accelerators.