RoCE Packet Sequence Acceleration via Partial Offload

Solution Overview

Problem

Current RoCE implementations face limitations in accelerating packet sequence transmission and reception over Converged Ethernet networks, particularly due to the need for complex hardware configurations and high costs associated with full offload solutions, which compromise performance and increase CPU utilization.

Innovation Solution

Implementing a partial offload of RoCE functionalities in both host software and adapter hardware, enabling the network adapter to generate transmit descriptors for packet sequences, perform Invariant CRC calculations, and validate received packets, thereby reducing processing latency and simplifying adapter configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If full offload of RoCE functionalities is implemented in hardware adapter, then packet transmission acceleration is improved, but device complexity and cost increase

Engineering Contradiction:

Improvepacket transmission speedVSAvoidadapter configuration complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent segments RoCE functionality into two parts: RoCE verbs interface handled by software and RoCE packet sequence generation handled by hardware adapter. This segmentation allows the hardware to accelerate packet transmission while the software maintains protocol compliance, avoiding the need for complete hardware offload and reducing adapter complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements partial offload where only the packet sequence generation and Invariant CRC validation are performed in hardware, while other RoCE functionalities remain in software. This partial hardware acceleration achieves performance improvement without requiring full hardware offload, thus reducing device complexity and cost.

Inventive Principle:

Principle #16Partial or excessive action

2Loss of time

If full offload of RoCE functionalities is implemented in hardware adapter, then processing latency is reduced, but cost increases

Engineering Contradiction:

Improveprocessing latencyVSAvoidimplementation cost

Core Design Contradiction:

Loss of timeVSEase of manufacture

Solution Approach 1:

The patent implements partial offload where only the packet sequence generation and Invariant CRC validation are performed in hardware, while other RoCE functionalities remain in software. This partial hardware acceleration achieves performance improvement without requiring full hardware offload, thus reducing device complexity and cost.

Inventive Principle:

Principle #16Partial or excessive action

3Device complexity

If RoCE protocol handling is fully implemented in host software, then adapter complexity is reduced, but CPU utilization increases

Engineering Contradiction:

Improveadapter configuration simplicityVSAvoidCPU utilization

Core Design Contradiction:

Device complexityVSUse of energy by moving object

Solution Approach 1:

The patent segments RoCE functionality into two parts: RoCE verbs interface handled by software and RoCE packet sequence generation handled by hardware adapter. This segmentation allows the hardware to accelerate packet transmission while the software maintains protocol compliance, avoiding the need for complete hardware offload and reducing adapter complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The hardware adapter performs Invariant CRC validation on received packets and generates transmit descriptors automatically, reducing the burden on the CPU. The adapter serves itself by handling these validation and generation tasks in hardware, freeing CPU resources for other tasks.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS9380134B2RoCE packet sequence acceleration

Publication Date: 2016.06.28 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

A method, network device and system for remote direct memory access (RDMA) over Converged Ethernet (RoCE) packet sequence acceleration are disclosed. The network device comprises one or more components for communicating with a host system. A network communication protocol, such as RoCE, is implemented by a combination of the one or more components and the host system.