Radio over Ethernet Timestamp Carrying for Clock Synchronization
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Solution Overview
Problem
Conventional Differential Clock Recovery (DCR) implementations in wireless fronthaul systems face limitations in synchronizing both frequency and phase across bidirectional paths, particularly in packet-based networks, due to unknown phase offsets and the inability to carry timestamps efficiently using existing standards like IEEE 1914.3 for Radio over Ethernet (RoE).
Innovation Solution
The use of a Global Reference Time for Differential Clock Recovery allows for constant time delay and phase preservation across packet networks, enabling frequency and phase synchronization across bidirectional paths. This is achieved by carrying timestamps separate from the 'orderInfo' field using a subtype of control packets and specific operational codes, such as Vendor Specific Data (VSD), and including flags to indicate whether the timestamp is for frequency only or phase-aligned Time of Day (ToD).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If SyncE is used to syntonize clocks on each node, then frequency synchronization is achieved, but phase offset remains unknown
Solution Approach 1:
The patent introduces a timestamp as an intermediary element that carries phase information through the packet network. The timestamp is inserted by the ingress node and processed by the egress node to recover the phase relationship between clocks, thereby mediating the loss of phase information during packet transmission
Solution Approach 2:
The ingress node performs preliminary action by calculating and inserting the timestamp into the packet before transmission. This timestamp contains the necessary phase information that will be used by the egress node to synchronize its clock phase with the ingress node, preventing phase information loss
2Ease of operation
If the 'orderInfo' field in RoE header is used for sequence numbering, then packet ordering is maintained, but timestamp carrying capability is lost
Solution Approach 1:
The patent segments the timing information into two separate components: the 'orderInfo' field continues to handle packet sequencing while a new 'timestamp' field carries the actual timing information. This segmentation allows both functions to operate independently without interfering with each other
Solution Approach 2:
The patent adds a new dimension to the RoE header structure by introducing a separate timestamp field. This dimensional expansion allows the system to carry both sequence numbers and timestamps simultaneously, resolving the conflict between maintaining packet ordering and carrying timestamp information
3Adaptability or versatility
If packet connectivity is used between RRH and BBU, then network flexibility is improved, but phase synchronization becomes difficult
Solution Approach 1:
The patent implements a feedback mechanism where the egress node uses the received timestamp to calculate the phase difference between its clock and the ingress node's clock. This feedback information is then used to adjust the egress node's clock phase, enabling precise phase synchronization over the flexible packet network
Solution Approach 2:
The patent replaces the traditional mechanical clock synchronization system with an electronic timestamp-based system. Instead of relying on physical clock signal transmission which is sensitive to propagation delays, the system uses electronic timestamps that can be precisely measured and used to calculate and correct phase differences
Data Source
AI summary
A node can include a clock; and mapper circuitry configured to determine a timestamp from the clock, and transmit the timestamp to a second node in a Radio over Ethernet (RoE) frame with the timestamp in a control subtype and with an operational code (opcode) that designates the timestamp is in the frame. The node can also include a demapper circuit configured to receive a second timestamp from the second node in a second RoE frame, and provide the second timestamp to a Differential Clock Recovery (DCR) circuit for adjustment of the clock to a second clock at the second node.