ROM Bit Cell Array Layout Generation Method
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Solution Overview
Problem
High-density ROM bit cell arrays face challenges with high coupling capacitance between bit lines and require complex readout logic, while their geometries operating close to the diffusion limit restrict design flexibility and the reuse of control circuitry.
Innovation Solution
A method for generating ROM bit cell array layouts that allows for a range of active area widths, enabling system designers to select based on performance characteristics like bit line capacitance and power consumption, while maintaining high density by positioning columns between their own bit and virtual ground lines, reducing diffusion constraints and increasing design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If adjacent bit cells share source/drain connections to achieve high density, then bit cell density is improved, but coupling capacitance between bit lines increases
Solution Approach 1:
The invention segments the bit cell array into columns, where each column has its own dedicated bit line and virtual ground line. This segmentation isolates the bit lines from each other, reducing coupling capacitance between them while maintaining high bit cell density within each column through shared source/drain connections.
2Area of stationary object
If bit lines are positioned close together to increase density, then area utilization is improved, but coupling capacitance between bit lines increases
Solution Approach 1:
The invention introduces virtual ground lines as intermediary elements positioned between adjacent bit lines. These virtual ground lines act as shields that reduce the coupling capacitance between bit lines while allowing the bit lines to be positioned close together for high area utilization.
3Quantity of substance
If geometries are operated close to diffusion limit to maximize density, then bit cell density is improved, but design flexibility is reduced
Solution Approach 1:
The invention makes the active area width a variable parameter that can be dynamically adjusted within a range, rather than being fixed at the diffusion limit. This allows designers to optimize for different performance characteristics (speed, power, area) while maintaining high density, thereby increasing design flexibility.
4Quantity of substance
If active area width is reduced to increase density, then bit cell density is improved, but performance characteristics such as speed and power are degraded
Solution Approach 1:
The invention changes the parameter of active area width from a fixed small value to a variable parameter that can be adjusted within a range. By optimizing this parameter, designers can achieve better power consumption and speed performance while maintaining high bit cell density, resolving the trade-off between density and performance.
Data Source
AI summary
A method of generating a ROM bit cell array layout including the steps of: inputting a predetermined memory architecture having a predetermined positioning of bit lines and virtual ground lines, the memory architecture including a plurality of columns of memory cells, each column of memory cells being located between associated bit lines and virtual ground lines. Adjacent memory cells in each column of memory cells share a common connection to either the associated bit line or the associated virtual ground line. The further steps of evaluating the width of active area of each of said columns of memory cells, in dependence on said predetermined positioning of bit lines and virtual ground lines; selecting a final width of active area in dependence on at least one performance characteristic associated with said final width of active area; and generating the layout according to said final width of active area.