ROM Bitcell Array Net Assignment Optimization
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Solution Overview
Problem
As integrated circuit features shrink, increased capacitance leads to degraded performance, current leakage, and decreased reliability due to high loads on bitlines in memory cell arrays, necessitating methods to reduce the load on these wires.
Innovation Solution
A design tool analyzes the layout of a ROM bitcell array to detect specific conditions, such as imbalanced connections between bitlines and ground, and applies optimization steps like swapping connections or removing connections to reduce the load on bitlines, thereby optimizing the layout and minimizing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integrated circuit features are shrunk to increase density, then functionality and manufacturing cost are improved, but capacitance increases causing degraded performance and increased current leakage
Solution Approach 1:
The patent applies parameter changes by modifying the connection configuration parameters of the ROM bitcell array. Specifically, it changes which terminal (bitline or ground) is connected to which node based on detected patterns, thereby altering the electrical characteristics of the bitlines to reduce capacitance and current leakage while maintaining the shrunk feature dimensions
2Quantity of substance
If the number of connections to bitlines is high, then storage capacity is improved, but load on bitlines increases causing increased capacitance and current leakage
Solution Approach 1:
The patent applies local quality by making different parts of the bitcell array have different connection configurations. Instead of uniformly connecting all nodes to bitlines, it selectively connects nodes to either bitline or ground based on local pattern detection (consecutive nets), thereby locally optimizing each region to reduce overall capacitance and current leakage while preserving storage capacity
Solution Approach 2:
The patent applies inversion by reversing the conventional connection approach. Rather than always connecting active nodes to bitlines, it inverts the connection strategy by connecting some nodes to ground when patterns are detected, thereby reducing the effective load on bitlines while maintaining the same storage functionality through alternative connection paths
Data Source
AI summary
Systems, apparatuses, and methods for reducing the load on the bitlines of a ROM bitcell array are described. The connections between nets of a ROM bitcell array may be assigned based on their programmed values using a traditional approach. Then, a plurality of optimizations may be performed on the assignment of nets to reduce the load on the bitlines of the array. A first optimization may swap the connections between ground and bitline for the nets of a given column responsive to detecting that the number of connections to the corresponding bitline is greater than the number of connections to ground for the given column. A second optimization may remove the connection of a net to a bitline if three consecutive nets of a given column are connected to the bitline.