NAND Flash ROM Block Erasure Protection via Transfer Transistor Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In NAND EEPROM flash memory, entire block erasure operations risk inadvertently erasing data from the ROM block, which stores essential operating information, as it is targeted by the erasure process and lacks distinct addressing.
Innovation Solution
The semiconductor memory device employs a control gate line driver circuit that grounds all control gate lines and uses transfer transistors to maintain the ROM block's word lines floating during erasure, preventing a potential difference between the floating gate and well, thus avoiding data erasure in the ROM block. This is achieved by keeping the transfer transistor of the ROM block off and ensuring the control gate lines remain at 0 V, while raising the well voltage for erasure in other blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If entire block erasure is performed to clear all data in the flash memory, then productivity is improved, but the ROM block data is accidentally erased
Solution Approach 1:
The flash memory blocks are segmented into two categories: normal blocks and ROM block. During entire block erasure, transfer transistors for normal blocks are turned on to connect control gate lines to ground, while the transfer transistor for the ROM block remains off, isolating it from the erasure operation. This segmentation allows selective erasure protection based on block type.
Solution Approach 2:
Different blocks are assigned different electrical properties during erasure. Normal blocks have their control gate lines connected to ground through transfer transistors, creating a potential difference for erasure. The ROM block maintains its control gate lines floating or at different potential, preventing the formation of erasure-condition potential difference. This local quality differentiation ensures the ROM block is excluded from erasure while other blocks are erased.
2Device complexity
If the ROM block is distinguished from other blocks by address only, then device complexity is reduced, but the ROM block cannot be protected during erasure
Solution Approach 1:
Transfer transistors are pre-configured and positioned for each block before erasure operations. The transfer transistor corresponding to the ROM block is designed to remain off during erasure, while others are turned on. This preliminary configuration of different transistor states enables automatic protection of the ROM block without requiring complex runtime address checking or control logic.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively prevents the accidental erasure of data in the ROM block during entire block operations by maintaining a potential difference only in the blocks intended for erasure, ensuring the integrity of the operating information stored in the ROM block.
Implementation Method 1
a control gate line driver circuit that grounds all control gate lines
Implementation Method 2
raising the well voltage for erasure in other blocks
Implementation Method 3
uses transfer transistors to maintain the ROM block's word lines floating during erasure, preventing a potential difference between the floating gate and well
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a semiconductor substrate which includes a well. A memory cell array includes memory cells each including a floating gate electrode above the well and a control gate electrode above the floating gate electrode, and is configured to write data in units of pages each including memory cells connected in series and to erase data in units of blocks each includes a plurality of the pages. A control gate line is selectively electrically connected to the control gate electrodes of at least one of the blocks. A first switching element includes a current path having ends connected to the control gate line and a ground end. The well is charged, and the first switching element is turned off before the end of the discharge of the well.