ROM Cell With Multiple Transistors For Low Power Storage
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Solution Overview
Problem
Conventional read-only memory (ROM) cells and arrays face inefficiencies in area usage, cost, and high power consumption due to high leakage, making them unsuitable for applications requiring significant on-chip memory.
Innovation Solution
The development of ROM cells and arrays that utilize MOS transistors coupled to multiple word lines and power lines, allowing for the storage of multiple logic states (bits) in a compact area, reducing power consumption, and enabling efficient data storage through selective voltage applications in different ROM modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional ROM cells are used, then simple structure is maintained, but area efficiency deteriorates and power consumption increases
Solution Approach 1:
The memory cell is segmented into multiple functional components: a first transistor for normal operation mode and a second transistor for high-voltage programming mode. This segmentation allows the cell to perform multiple functions with a single structure, improving area efficiency while maintaining operational simplicity through functional decomposition.
Solution Approach 2:
The memory cell structure is designed to be universal, serving both as a normal operation ROM cell and as a high-voltage programming cell. The same physical structure performs different functions based on voltage application, eliminating the need for separate cell types and reducing overall area requirements.
2Ease of manufacture
If conventional ROM cells are used, then manufacturing simplicity is maintained, but cost increases due to area inefficiency
Solution Approach 1:
The patent merges the functionality of multiple ROM cells into a single cell structure by combining the first and second transistors within one cell. This merging reduces the total number of cells needed, thereby reducing area while maintaining manufacturing simplicity through the use of standard CMOS processes.
Solution Approach 2:
The cell structure utilizes parameter changes in voltage application to switch between operational modes. By applying different voltage levels (normal operation voltage vs. high programming voltage), the same physical structure achieves different functions, maintaining manufacturing simplicity while improving area efficiency.
3Use of energy by stationary object
If conventional ROM cells are used, then structural simplicity is maintained, but power consumption increases due to high leakage
Solution Approach 1:
The patent extracts the high-voltage programming function from the normal operation function by using a separate second transistor that is only activated during programming. This extraction allows the first transistor to remain in a low-leakage state during normal operation, reducing power consumption while adding minimal complexity through the inclusion of a single additional transistor.
Data Source
AI summary
A read only memory (ROM) having a first row of ROM cells, a first conductive line along the first row of ROM cells, and a second conductive line along the first row of ROM cells. The ROM cells of the first row of ROM cells are selectively coupled during programming to the first conductive line and the second conductive line so that in a first mode of the ROM the first row of ROM cells provide a first combination of logic highs and logic lows and in a second mode of the memory the first row of ROM cells provide a second combination of logic highs and lows independent of the first combination of logic highs and logic lows.