ROM Debug Circuitry Boot Error Capture

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Solution Overview

Problem

Current integrated circuit (IC) devices can only capture two boot errors during the boot process, leading to multiple iterations being required for debugging, which increases processing time and resource consumption.

Innovation Solution

A processing system with ROM debug circuitry captures and stores error and debug information in non-circular buffers, allowing for the retention of all error entries without overwriting, reducing the need for multiple boot iterations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If only two boot errors are captured during the boot process, then the device complexity is reduced, but the debugging efficiency deteriorates requiring multiple boot iterations

Engineering Contradiction:
Improveerror capture mechanismVSAvoiddebugging efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The error buffer is segmented into multiple entry locations (first through fourth entries) that can independently store different error information. This segmentation allows simultaneous storage of multiple error occurrences without requiring a single large buffer, thus maintaining manageable device complexity while improving debugging efficiency by capturing all errors in one boot iteration.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The error buffer is designed to serve multiple functions: it can store different types of error information (authentication errors, encryption errors, boot process errors) and can be accessed by different debugging mechanisms. This multi-functionality allows the same buffer structure to capture comprehensive error data without increasing device complexity proportionally.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Loss of information

If multiple boot iterations are performed for debugging, then complete error information is obtained, but the processing time increases

Engineering Contradiction:
Improveerror information completenessVSAvoiddebugging time
Core Design Contradiction:
Loss of informationVSLoss of time

Solution Approach 1:

The error buffer is pre-configured with multiple entry locations during device manufacturing, ready to capture error information without requiring additional runtime operations. This preliminary preparation ensures that all errors occurring during a single boot process are captured immediately, eliminating the need for multiple boot iterations and reducing debugging time while maintaining complete error information.

Inventive Principle:
Principle #10Preliminary action

3Loss of information

If all error entries are retained without overwriting, then debugging thoroughness is improved, but the memory resource consumption increases

Engineering Contradiction:
Improveerror entry retentionVSAvoidmemory resources
Core Design Contradiction:
Loss of informationVSQuantity of substance

Solution Approach 1:

The error buffer uses an asymmetric structure where different entry locations (first through fourth entries) serve different purposes: some entries are designed to be overwritten under specific conditions while others are preserved. This asymmetric design allows the system to retain critical error information that would otherwise be lost, improving debugging thoroughness without requiring a proportionally larger memory resource allocation.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS20240220365A1Error and debug information capturing for a boot process
Publication Date: 2024.07.04 XILINX INC
  • US20240220365A1 patent drawing
  • US20240220365A1 patent drawing
  • US20240220365A1 patent drawing

AI summary

Error and debug information is saved during a boot process. A read only memory (ROM) debug circuitry (RDC) obtains detected errors within ROM code during a boot process. Error information is generated and stored within a first memory element. The error information includes entries. Each of the entries is associated with a respective one of the errors. Debug information is generated and stored by the RDC within a second memory element. The debug information is associated with the boot process. Further, the method includes outputting, via test circuitry of the processing system, the error information and debug information based on a testing instruction.