ROM Cell Gate Window Structure for High Density Read Speed
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Solution Overview
Problem
As integration scale decreases in CMOS read-only memory technology, the width of doped regions in memory cells reduces, leading to a decrease in reading current and an increase in reading time.
Innovation Solution
The design of memory cells with storage transistors featuring gates formed as windows on the substrate, where the inner contour delimits a central drain region and the outer contour delimits source regions, increasing the effective width of the transistors and enhancing the drain-source current without significantly increasing the substrate area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integration scale decreases in CMOS read-only memory technology, then memory density increases, but reading current decreases and reading time increases
Solution Approach 1:
The gate structure transitions from a conventional planar configuration to a three-dimensional window-shaped structure with vertical extensions into the substrate. This dimensional change allows the gate to encompass both source and drain regions within its perimeter, effectively increasing the transistor width without expanding the lateral footprint of the memory cell, thereby maintaining high density while improving reading current and speed
2Area of stationary object
If integration scale decreases, then memory cell area reduces, but transistor width reduces leading to lower reading current
Solution Approach 1:
The gate is designed as a window structure extending vertically into the substrate, allowing it to control a larger effective transistor width within the same lateral memory cell area. The gate's inner contour delimits the drain region while its outer contour delimits the source region, creating a three-dimensional control volume that increases reading current without expanding the two-dimensional cell footprint
Solution Approach 2:
The drain region is nested within the gate structure, with the gate's inner contour forming the drain region boundary. This nesting arrangement allows the gate to efficiently control the transistor channel while maximizing the use of available space within the memory cell, thereby maintaining compact cell area while achieving enhanced reading current through increased effective width
Data Source
AI summary
An integrated circuit memory of the read-only memory type includes at least one memory cell. Each memory cell includes a storage transistor realized in a semiconductor substrate and presenting a source connected to a reference potential, a gate connected to an electrically conductive word line, and a drain connected to an electrically conductive bit line by an optional connection depending on whether the memory cell is assigned the value 0 or 1. The storage transistor of each memory cell includes a gate formed on the substrate, in the form of a window whose inner contour delimits a central drain region in the substrate, and whose outer contour delimits at least one source region in the substrate.