ROM Device Structure Leakage Current Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing ROM devices and fabrication methods are not entirely satisfactory in reducing leakage current between adjacent transistors, which affects the performance of read-only memory cell arrays.
Innovation Solution
The ROM cell array structure incorporates isolation transistors configured to remain in the 'off' state, eliminating the need for shallow trench isolation structures and using a thickness difference in work function layers between gate and isolation structures to achieve a higher threshold voltage, thereby reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shallow trench isolation structures are used to isolate adjacent transistors, then isolation between transistors is achieved, but device complexity and manufacturing steps increase
Solution Approach 1:
The patent extracts and eliminates the shallow trench isolation structure from the device architecture. Instead of adding isolation structures between transistors, the invention uses the substrate itself as the isolation medium by forming transistors in separated active regions, thereby reducing device complexity while maintaining effective isolation.
Solution Approach 2:
The substrate serves multiple functions: it provides mechanical support, electrical isolation between active regions, and the foundation for transistor formation. By making the substrate perform the isolation function, the patent eliminates the need for separate isolation structures, reducing overall device complexity.
2Reliability
If work function layer thickness is increased to achieve higher threshold voltage, then leakage current is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the thickness parameter of the work function layer to optimize threshold voltage. By forming the work function layer with controlled thickness (e.g., 1-10 nm range), the invention achieves higher threshold voltage and reduced leakage current while managing manufacturing precision through advanced deposition techniques.
Solution Approach 2:
The gate structure uses composite materials with different work function characteristics. By combining materials with appropriate work functions in a layered structure, the patent achieves precise threshold voltage control without requiring extremely tight thickness tolerances, as the composite nature provides tuning flexibility.
3Reliability
If isolation transistors are maintained in 'off' state to reduce leakage, then leakage current between adjacent transistors decreases, but device operation complexity increases
Solution Approach 1:
The isolation transistors are designed and configured during fabrication to remain in the 'off' state during normal operation. This preliminary configuration establishes the isolation function at the device structure level, eliminating the need for dynamic control during operation and avoiding increased operational complexity.
Solution Approach 2:
The isolation transistors automatically maintain the isolation function through their inherent design characteristics (threshold voltage, gate structure) without requiring external control signals or complex control circuits. The structure itself provides the isolation service, simplifying operation.
Data Source
AI summary
A read-only memory (ROM) structure is provided. The ROM device structure includes a first gate structure formed over a substrate, and the first gate structure includes a first work function layer with a first thickness. The ROM device structure includes an isolation structure formed over the substrate, and the isolation structure is adjacent to the first gate structure. The isolation structure includes a second work function layer with a second thickness, and the second thickness is larger than or smaller than the first thickness. The ROM device structure also includes a first contact structure formed over the substrate, and the first contact structure is between the first gate structure and the isolation structure.


