ROM Leakage Reduction Circuit via Intermediary Transistor Control
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Solution Overview
Problem
Read-only memory (ROM) devices experience parasitic power loss due to leakage current during idle conditions, which affects their efficiency and performance.
Innovation Solution
Incorporating a leakage current reduction circuit that generates a voltage differential less than the precharge voltage, reducing static current draw by acting as a 'floating ground' when enabled, and returning to the original voltage differential during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a voltage bias is applied at the bit line during idle condition, then the bit line is pre-charged to a first voltage level, but a large voltage difference across the transistor creates static current draw (leakage current)
Solution Approach 1:
The patent introduces a leakage current reduction circuit that acts as an intermediary between the bit line and ground. This circuit includes a first transistor connected in parallel with the memory cell transistor, controlled by a leakage current reduction signal. When enabled, this intermediary transistor provides an alternative current path that reduces the voltage difference across the memory cell transistor, thereby reducing leakage current while maintaining bit line precharge functionality.
Solution Approach 2:
The patent dynamically changes the electrical parameters of the circuit by controlling the leakage current reduction circuit. When the leakage current reduction signal is asserted, the circuit modifies the voltage differential across the memory cell transistor from a large value (during idle) to a reduced value, thereby changing the current flow characteristics and reducing parasitic power loss.
2Device complexity
If a single transistor configuration is used for ROM cells, then the memory structure is compact and fabrication is simple, but leakage current occurs during idle conditions
Solution Approach 1:
The patent segments the current path by introducing a parallel transistor configuration. Instead of relying on a single transistor, the memory cell transistor is divided into two parallel paths: one through the original memory cell transistor and another through the leakage current reduction transistor. This segmentation allows independent control of each path, enabling leakage reduction without fundamentally changing the core single-transistor memory cell design.
Solution Approach 2:
The leakage current reduction transistor serves as an intermediary element that addresses the leakage issue without requiring a complete redesign of the memory cell structure. It is connected in parallel and controlled by a separate signal, allowing it to mediate the current flow and reduce leakage while preserving the simplicity of the original single-transistor configuration.
3Speed
If the bit line is pre-charged during idle condition, then the memory is ready for quick read operations, but static current draw increases
Solution Approach 1:
The patent implements periodic control of the leakage current reduction circuit based on the operational state of the memory. The leakage current reduction signal is de-asserted during active read operations (when fast access is needed) and asserted during idle conditions (when leakage reduction is prioritized). This periodic action optimizes the balance between speed and power consumption based on operational requirements.
Solution Approach 2:
The patent makes the circuit dynamics by enabling the leakage current reduction circuit to adapt its behavior based on operational conditions. The circuit dynamically adjusts the voltage differential across the memory cell transistor by controlling the leakage current reduction transistor, allowing it to reduce leakage during idle states while maintaining full performance during active read operations.
Data Source
AI summary
A method for performing a read operation of a memory block of a read-only memory array, wherein the method comprises first enabling bit line precharge circuitry of the memory block, (thereby precharging one or more bit lines of the memory block to a first voltage level), enabling a word line of one or more addressed memory cells of the memory block, enabling a leakage current reduction circuit of the memory block, thereby generating across the addressed memory cells a first voltage differential equal to the first voltage level; subsequently discharging the addressed memory cells; disabling the word line of the one or more addressed memory cells; disabling the bit line precharge circuitry; and disabling the leakage current reduction circuit, thereby generating across the one or more addressed memory cells a second voltage differential that is equal to less than the first voltage differential.