ROM Matrix Differential Sensing Without Reference Bit Line

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Solution Overview

Problem

Conventional ROM matrices with differential sense amplifiers require careful capacitance balancing and a reference bit line to distinguish data values, which is prone to interference and power consumption, and lacks the flexibility to operate without a reference bit line.

Innovation Solution

A ROM matrix with a differential sense amplifier that uses a two-phase readout process, where charge sharing is established and then severed, allowing the sense amplifier to amplify signals without a reference bit line, eliminating the need for capacitance balancing and reducing power consumption by integrating the reference circuit in the memory matrix periphery.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a reference bit line is used to provide reference signal to the differential sense amplifier, then reliable differential sensing can be achieved, but the reference bit line takes up space in the integrated circuit and consumes power

Engineering Contradiction:
Improvereliable differential sensingVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The invention extracts the reference signal generation function from the bit line structure itself. Instead of using a dedicated reference bit line that runs parallel to all bit lines, the reference signal is generated locally at the sense amplifier inputs by coupling each sense amplifier input to a reference voltage through a resistor. This eliminates the need for a separate reference bit line infrastructure, thereby reducing space consumption and power consumption while maintaining reliable differential sensing.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If a reference bit line is used to generate reference signal, then differential sensing can be performed, but the reference bit line is prone to interference and requires careful capacitance matching

Engineering Contradiction:
Improvedifferential sensing capabilityVSAvoidinterference and capacitance matching requirements
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The invention removes the reference bit line from the system entirely. Instead of relying on a shared reference bit line that is susceptible to interference and requires precise capacitance matching with all bit lines, each sense amplifier receives its reference signal independently through local resistive coupling to a reference voltage. This eliminates the interference problems and capacitance matching requirements associated with shared reference bit lines.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The invention introduces resistors as intermediary elements between the reference voltage and each sense amplifier input. These resistors serve as mediators that provide a stable reference signal without requiring direct capacitive coupling, thereby eliminating the need for capacitance matching between the reference line and bit lines, and reducing susceptibility to interference.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If capacitance balancing is performed between bit line and reference circuit, then differential sensing accuracy is improved, but device complexity and design difficulty increase

Engineering Contradiction:
Improvedifferential sensing accuracyVSAvoidcapacitance balancing requirements
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The invention extracts the reference signal delivery mechanism from the capacitive coupling approach to a resistive coupling approach. By using resistors to couple the reference voltage to each sense amplifier input, the invention eliminates the need for capacitance balancing between bit lines and reference circuits, thereby reducing design complexity while maintaining differential sensing accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

4Reliability

If a reference bit line extends along the entire memory matrix in parallel with bit lines, then reference signal is provided to all sense amplifiers, but space requirements increase

Engineering Contradiction:
Improvereference signal distributionVSAvoidspace in integrated circuit
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The invention removes the physical reference bit line that would extend parallel to all bit lines across the memory matrix. Instead, each sense amplifier generates its own reference signal locally through resistive coupling to a reference voltage, eliminating the need for a dedicated reference bit line infrastructure and thereby significantly reducing the space required in the integrated circuit.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Each sense amplifier serves itself by generating its own reference signal locally through resistive coupling to the reference voltage, rather than relying on a shared reference bit line. This self-service approach eliminates the need for a distributed reference bit line network, reducing space requirements while ensuring reliable reference signal distribution to all sense amplifiers.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS7554831B2Integrated circuit device with a ROM matrix
Publication Date: 2009.06.30 CALLAHAN CELLULAR LLC
  • US7554831B2 patent drawing
  • US7554831B2 patent drawing
  • US7554831B2 patent drawing

AI summary

A read only memory matrix in an integrated circuit contains data transistors coupled to both the bit lines and the word lines in data dependent ones of the cells of the matrix. A differential sense amplifier has a first input coupled to a bit line, a second input coupled to a reference circuit and a control input for controlling activation and deactivation of amplification by the sense amplifier. A coupling circuit controllably permits charge sharing between a selectable one of the bit lines and the first input. A timing circuit is arranged to signal operation in a first phase, when the word lines have selected a row of the matrix, followed by a second phase. The timing circuit controls the coupling circuit to permit charge sharing between the input and the selectable one of the bit lines in the first phase. In the second phase the timing circuit controls the coupling circuit to prevent charge sharing, makes the reference circuit deactivate driving the reference voltage, and subsequently activates amplification by the differential sense amplifier. Preferably the timing circuit contains a dummy bit line and a trigger circuit for triggering the second phase when a potential swing on the dummy bit line exceeds a threshold value.