ROM Cells Integrated in NVM Array for Secure Code Storage
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Solution Overview
Problem
Existing non-volatile memory (NVM) cell arrays are not suitable for securely storing read-only memory (ROM) code due to the risk of accidental overwriting or hacking, and dedicated ROM structures on the same chip are easily identifiable and increase manufacturing complexity and cost.
Innovation Solution
Integrating ROM cells within the NVM array using similar structures, where ROM cells have distinct configurations such as omitting the floating gate, forming a single control gate, and using a dummy gate to ensure fixed '1' or '0' states by controlling bit line contacts or substrate implantations, making them indistinguishable from NVM cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If NVM cells are used to store code, then the code can be re-programmed and updated, but the code becomes vulnerable to accidental overwriting and hacking
Solution Approach 1:
The memory array is segmented into two distinct types of memory cells: NVM cells with floating gates for re-programmable code, and ROM cells without floating gates for secure, immutable code. This segmentation allows simultaneous presence of both updateable and secure code storage within the same array structure.
Solution Approach 2:
Different regions of the memory array have different structural qualities - some regions have floating gates (NVM cells) while others lack floating gates (ROM cells). This local differentiation enables each region to serve its specific function: re-programmability where needed, security where required.
2Reliability
If a dedicated ROM structure is provided separate from the NVM array, then code security is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The ROM cells and NVM cells are merged into a single memory array structure, sharing common source regions, drain regions, select gates, and control gates. The only structural difference is the presence or absence of floating gates, which simplifies manufacturing by eliminating the need for separate ROM processing steps.
Solution Approach 2:
The memory array structure serves multiple functions: it stores both re-programmable code (in NVM cells) and secure immutable code (in ROM cells) using the same fundamental cell architecture, select gate control, and readout mechanisms, thereby achieving security without sacrificing manufacturing efficiency.
3Reliability
If a dedicated ROM structure is provided separate from the NVM array, then code security is improved, but the ROM structure becomes easily identifiable and subject to hacking
Solution Approach 1:
The memory array exhibits local quality variation where individual cells differ in structure (presence/absence of floating gates) but the overall array maintains uniform architecture. This makes it difficult to identify which specific cells are ROM cells versus NVM cells, as they appear identical at the array level and share the same external interfaces.
Solution Approach 2:
The ROM cells and NVM cells maintain homogeneous appearance and external characteristics within the memory array, using the same source/drain regions, select gates, and control gates. This homogeneity obscures the identity of secure code regions from potential hackers who would need to physically analyze each cell to distinguish ROM from NVM.
4Reliability
If ROM cells are formed with distinct structures from NVM cells, then code security is improved, but manufacturing complexity increases
Solution Approach 1:
The floating gate component is extracted from the ROM cell structure while remaining in the NVM cell structure. This selective extraction creates the desired security differentiation (no floating gate = ROM) while maintaining manufacturing simplicity, as the floating gate formation steps are simply omitted for ROM cells during the same fabrication process.
Data Source
AI summary
A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.