ROM Redundancy Circuit for Built-In Self-Test Bit Repair
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Solution Overview
Problem
In deep submicron technology, manufacturing read-only memory (ROM) with sufficient redundancy to repair bit failures is challenging due to the difficulty in identifying and addressing failed bits without external diagnostic testers, as existing ROM built-in-self-test (BIST) techniques do not determine the location of bit failures effectively.
Innovation Solution
A read-only memory (ROM) with redundancy is designed, incorporating a programmable array coupled to a repair circuit with word address match logic, tri-state buffers, and error correction code (ECC) logic, which enables built-in-self-test (BIST) to identify and repair bit failures within the ROM, reducing the need for external testers and improving repair efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ROM BIST techniques are used to detect bit failures, then detection capability is improved, but the ability to identify the location of failing bits deteriorates
Solution Approach 1:
The patent introduces an intermediary diagnostic process that bridges the gap between ROM BIST detection and precise location identification. The MISR (Multiple Input Signature Register) captures the signature of failed bits, and this signature is then fed into an external diagnostic tester that acts as an intermediary to decode the signature and identify the exact location of failing bits without directly testing each bit individually.
Solution Approach 2:
The patent implements a feedback mechanism where the output of the MISR (which contains compressed information about failed bits) is fed back into the diagnostic system. This feedback loop allows the system to use the compressed signature information to iteratively identify and locate failing bits, transforming the initial detection output into precise location information.
2Ease of repair
If redundant elements are used to repair bit failures, then repair capability is improved, but data routing complexity increases
Solution Approach 1:
The patent segments the repair process into distinct functional blocks: address matching logic, tri-state buffer control, and data routing paths. Each redundant repair element is divided into independent segments that can be individually controlled and activated. This segmentation allows the system to repair multiple bits simultaneously while managing routing complexity through modular organization.
Solution Approach 2:
The patent employs dynamic control of tri-state buffers that enable or disable redundant repair paths based on the detected failure locations. The address match logic dynamically activates only the necessary redundant elements corresponding to failed bits, rather than permanently enabling all redundant paths. This dynamic activation reduces the effective routing complexity during operation while maintaining full repair capability.
3Reliability
If entire words are replaced in the address space, then repair coverage is improved, but routing requirements increase
Solution Approach 1:
The patent applies local quality by providing different repair granularities for different locations in the address space. Instead of uniformly replacing entire words throughout the ROM, the system uses address match logic to identify specific failing bits and activates only the local redundant elements corresponding to those specific locations. This allows precise local repair without the overhead of global word replacement routing.
Solution Approach 2:
The patent implements partial action by activating only the necessary portion of redundant repair elements based on the actual failure pattern. The address match logic compares the failed address with stored redundant element addresses and activates only the matching redundant elements. This partial activation approach provides sufficient repair coverage for the actual failures while avoiding the excessive routing requirements of activating all redundant elements or replacing entire words.
Data Source
AI summary
A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.