ROM Self-Test Signatures for Faster Error Detection

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Solution Overview

Problem

Conventional BIST methods for testing Read-Only Memory (ROM) are time-consuming due to the need to access and compare every memory location, which is not feasible for ROMs with fixed data content.

Innovation Solution

A fast ROM test method using a variable number of read operations with extended and at-speed cycles, combined with modulo addition/subtraction or XOR operations to generate a signature without requiring complete ROM data access, allowing for efficient error detection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional BIST methods are used to test ROM, then complete test coverage is achieved, but test time becomes excessively long

Engineering Contradiction:
Improvetest coverageVSAvoidtest time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial action by performing a limited number of read operations (e.g., 2-4 reads) at extended speed rather than reading the entire ROM. This partial testing approach achieves sufficient error detection coverage without the excessive time cost of complete ROM verification, directly resolving the contradiction between thorough testing and time consumption.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent changes the read cycle time parameter by performing reads at an extended speed (longer read cycle) rather than normal speed. This parameter change allows each read operation to retrieve multiple bytes simultaneously, significantly reducing the total number of operations needed and thereby reducing overall test time while maintaining adequate coverage.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If complete ROM data is accessed for testing, then accurate error detection is achieved, but test complexity increases

Engineering Contradiction:
Improveerror detection accuracyVSAvoidtest complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts only the essential information needed for error detection by performing a limited number of strategic read operations rather than accessing complete ROM data. By extracting sufficient samples (e.g., reading 2-4 locations at extended speed), the method achieves accurate error detection without the complexity of processing and comparing entire ROM contents.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses partial action by performing fewer read operations than would be required for complete data access. This partial testing approach maintains error detection accuracy for the most critical fault types while significantly reducing test complexity by avoiding the need to process every byte in the ROM.

Inventive Principle:
Principle #16Partial or excessive action

3Loss of time

If fast BIST algorithms are applied, then test time is reduced, but they cannot be used for ROM with fixed data content

Engineering Contradiction:
Improvetest timeVSAvoidapplicability to ROM
Core Design Contradiction:
Loss of timeVSAdaptability or versatility

Solution Approach 1:

The patent creates a universal testing method that works for both RAM and ROM by adapting the fast BIST concept. The method uses a configurable number of read operations that can be adjusted based on ROM size and requirements, making it universally applicable to different ROM implementations while maintaining fast test times. The approach is versatile enough to handle various ROM configurations without requiring complete data access.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260004864A1Fast, low area self-test for read-only memory
Publication Date: 2026.01.01 STMICROELECTRONICS INT NV
  • US20260004864A1 patent drawing

AI summary

Methods for performing a fast read-only memory (ROM) test are disclosed. In the first method, a signature is generated by performing a first set of N read operations utilizing an extended read-cycle, followed by a second set of N read operations utilizing an at-speed read-cycle, where N is an integer greater than or equal to 2. The retrieved data is combined using modulo addition and subtraction operations and stored in a signature register. In the second, a signature is generated by performing two read operations utilizing an extended read-cycle, followed by two read operations utilizing an at-speed read-cycle. The retrieved data is combined using exclusive OR (XOR) operations and stored in a signature register. The final signature is compared to a predetermined value to determine if any errors were detected. Both methods provide a robust test capable of detecting various ROM errors while minimizing test time and complexity.