ROM Array Shared Bit-Line Architecture for High Density
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Solution Overview
Problem
Current ROM architectures face challenges in increasing capacity and efficiency due to the high number of bit-cells required, which leads to increased chip cost and reduced density, especially in devices like industrial control systems and mobile devices.
Innovation Solution
The implementation of a ROM memory array with shared bit-lines, where each bit-cell is associated with multiple bit-lines and shares additional bit-lines with adjacent cells, reducing the overall number of bit-cells needed and enhancing density without using multi-level approaches or additional masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional ROM architectures use one bit-line per bit-cell, then the structure is simple and easy to manufacture, but the density is low and chip cost increases
Solution Approach 1:
The patent merges multiple bit-lines into shared bit-lines that serve multiple bit-cells. Specifically, bit-lines are shared between adjacent bit-cells in the same column, allowing one bit-line to read data from multiple bit-cells simultaneously. This reduces the total number of bit-lines required and increases memory density without complicating the basic bit-cell structure.
Solution Approach 2:
The patent makes bit-lines universal by enabling them to serve multiple functions - each bit-line can be used to read data from multiple different bit-cells depending on which word-line is activated. This multi-functionality allows the same physical bit-line infrastructure to support a larger number of bit-cells, thereby increasing density while reusing existing circuitry.
2Quantity of substance
If more bit-cells are added to increase memory capacity, then storage capacity increases, but chip cost increases and manufacturing yield decreases
Solution Approach 1:
By merging bit-line resources through sharing, the patent achieves higher memory capacity without proportionally increasing the number of physical bit-lines. This reduces the overall component count and interconnect complexity, leading to improved manufacturing yield and reduced chip cost while still achieving the desired storage capacity.
3Ease of operation
If traditional bit-line allocation is used, then each bit-cell has dedicated access, but the overall device density is reduced
Solution Approach 1:
The patent implements a virtual copying mechanism where the same bit-line can be logically associated with multiple bit-cells through the activation of different word-lines. When a specific word-line is activated, the bit-line effectively copies its reading function to the corresponding bit-cell, enabling dedicated access semantics while sharing physical resources to increase density.
Data Source
AI summary
Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with one or more other bit-lines of the memory array. Each shared arrangement is structured to operably store a plurality of bits.